VME Readout At and Below the Conversion Time Limit
The achievable acquisition rates of modern triggered nuclear physics experiments are heavily dependent on the readout software, in addition to the limits given by the utilized hardware. This paper presents an asynchronous readout scheme that significantly improves the livetime of an otherwise synchronous triggered VME-based data acquisition system. A detailed performance analysis of this and other readout schemes, in terms of the basic data transfer operations, is described. The performance of the newly developed scheme as well as synchronous schemes on two systems has been measured. The measurements show excellent agreement with the detailed description. For the second system, which previously used a synchronous readout, the deadtime ratio is at a 20 kHz trigger request frequency reduced by 30 % compared to the nearest contender, allowing 10 % more events to be recorded in the same time. The interaction between the network and readout tasks for single-core processors is also investigated. A livetime ratio loss of a few percent can be observed, depending on the size of the data chunks given to the operating system kernel for network transfer. With appropriately chosen chunk size, the effect can be mitigated.
Most modern nuclear physics experiments have detectors, front-end electronics, computer control, and network. The role of the front-end electronics is to digitize the detector signals such that they can be analyzed. Modular front-end electronics are typically housed in crates such as NIM, FASTBUS, CAMAC or VME, where the latter three also contain a bus on the crate backplane. A typical crate configuration consists of a group of front-end modules together with a controlling single board computer (SBC). The task of the SBC is to acquire data from the front-end modules and transfer it over the network to permanent storage and online analysis. The speed, overhead, and serialization effects of this transfer naturally limit the maximum achievable acquisition rate, characterized by the rate of accepted triggers.
This article will focus on VME-based  readout systems. The purpose is not to introduce new electronics. Instead, we aim at better utilizing the commercially available modules by generally introducing an extreme asynchronous multi-event readout scheme called shadow readout. The main speedup is achieved by almost completely decoupling the readout from the conversion sequence, thereby significantly lowering the readout overhead associated with each accepted trigger. In addition, the coincidence information leading to each trigger is recorded, thus not sacrificing event selection flexibility for speed. It is also shown that the remaining system deadtime can be accurately described based on the timing of basic data transfer operations.
The article is structured in the following way: First, the existing solutions are reviewed, and the necessary concepts in order to model the deadtime and efficiency of the different readout modes are introduced. This is followed by a brief discussion of various modes of VME access. We then describe our implementation and the caveats that arise from having a single-core SBC. Finally, we benchmark the improved readout scheme versus the other strategies on two different systems.
Ii Existing solutions
With CAMAC systems, LeCroy introduced fast readout using the FERA bus in the early 80s, which transfers data at 10 Mword/s (16-bit) . With conversion times, at that time, usually around /channel or for an 8-channel module, a crate with 50 words of data per event (after zero-suppression) would be read out in . Thus the readout overhead was much smaller than the conversion time.
FASTBUS modules , even though known for their high channel density and thus long total module conversion times, usually had multi-event buffers, allowing readout of previous events while converting new ones, completely hiding the readout.
The current state of affairs for VME based readout systems is that nearly all front-end modules are capable of storing multiple converted events in an internal memory buffer. The Daresbury MIDAS  and BARC-TIFR LAMPS  utilize these buffers fully to decouple readout from conversion. In this scheme, the module buffers are continuously emptied by the crate controller. Only if a module becomes full, will it assert a long busy; halting the acquisition until the SBC empties a part of the module buffer. This mode, however, is only available for the Silena S9418 front-end modules in MIDAS , and the LAMPS is hampered by large overhead times in the associated CAEN VME controller .
However, the above systems are exceptions, and the multi-event buffers are often not utilized to their full extent, or not at all. Fig. 1 illustrates the three principal modes in which a readout system can be operated when front-end modules have buffers. In the simplest case, the front-end acquires an event and waits for the readout to transfer it. This is called single-event mode. Typically, the data transfer will take significantly longer than the conversion time due to various overheads. These overheads can be partially amortized by filling the front-end buffers before performing a readout. This is called multi-event mode. However, the number of events that can be acquired in one go is limited to the shallowest buffer. To the best of our knowledge, common general-purpose nuclear physics data acquisition systems, such as MIDAS (PSI/TRIUMF) , MBS (GSI) , and RIBFDAQ (RIKEN) , use versions of these schemes, where the SBC must interact with the trigger logic for every readout round.
In order to minimize the transfer times, when running in single event mode, the Mountable Controller (MOCO)  was recently developed at RIKEN. This innovative design is an adapter board with an FPGA and a USB interface which is installed between a front-end module and the VME crate backplane. With MOCO installed, the data lines of the front-end module are not connected to the backplane. Instead, the FPGA communicates directly with the front-end module. The FPGA can then transfer the data to the controlling computer via USB. The two main benefits of this solution are cost and parallelization of the readout of multiple modules.
In this article, we will show that a continuous readout mode, operating beyond the depth of the multi-event buffers, can be applied generally, without introducing new electronics.
Iii Deadtime modeling
In this section, we develop a framework to describe the deadtime of a system. This model will be used to analyze the systems in Section VII.
Assume that the front-end electronics and readout system is provided with a stream of Poisson-distributed trigger requests, with an average frequency , of which it can accept some frequency . The livetime ratio is the fraction of accepted trigger requests:
is the amount of time per event that the system is blocked. The last equality assumes the deadtime to be non-extending, and the formula is derived in . The livetime ratio is related to the deadtime ratio via .
We carefully differentiate between a system in deadtime and the deadtime ratio, . A system in deadtime rejects events while the deadtime ratio is the fraction of rejected events. The same differentiation is made between the livetime and the livetime ratio, .
It is often necessary to consider a distinct contribution to the total system deadtime: busy. Busy signals come from front-end modules, and is also autonomously released by those. It is generally asserted during gate and conversion, and when the data buffer of a module is full. The more regular deadtime is initiated by the trigger logic, and removed by the SBC readout software. As far as trigger acceptance is concerned, both have the same effect: inhibit triggers.
While running, the system must perform the following tasks (with associated processing times):
apply the gate of each accepted event, ;
convert the event, ;
poll for data, (per poll);
readout overhead (e.g. determine data amount), ;
read data, ;
check module synchronicity, ;
transfer data over the network, .
The two first are handled by the front-end electronics, the other by the SBC. Some of the tasks happen during either live- or deadtime, depending on the design of the system. Thus the minimal deadtime ratio is given by the fraction of time modules are busy converting data:
If the system is designed such that it reads one single event at a time, and will not accept new events while reading data, then the readout time is , since the system must poll for data, determine the amount of data, read the data and check for synchronicity. Since the likelihood that a random trigger request occurs during deadtime is simply the total fraction of time the system will not accept triggers, the deadtime ratio is
However, this scheme suffers the overhead of for every event. If the front-end electronic modules have buffers of a certain depth , then the cost of polling, general readout overhead, and synchronization can be amortized:
This mode of operation is commonly referred to as multi-event mode with the former called single-event mode. In this case, can often also be reduced as the larger amounts of data per transfer may profit from faster transfer modes.
If, however, the system can simultaneously accept new events and transfer data, then may be further reduced:
is the number of events accepted before synchronicity is checked and is the average number of events remaining to read out during deadtime. The fraction of events read during deadtime is thus . but will typically only be a few events. It should be noted that for many older modules is typically 32 or less, while newer modules might store a few hundred events. However, can in principle be made arbitrarily large, and thus the deadtime can be reduced to the busy time, .
The above has not considered the available data transfer bandwidth, which may also limit the maximum event rate that can be accepted:
In practice, the achievable frequency will be slightly lower due to various other overheads such as network transfer. Above this request frequency, the livetime ratio just deteriorates while no more events are accepted and is simply described:
For shadow readout, is expected to be approximately equal to the gate and conversion time . The livetime characteristics of the different readout schemes are illustrated in Fig. 2, where also the hard limit nature of is clearly seen.
In practice, the transition between the two domains is not sharp, due to interplay among the different saturating mechanisms, which is not investigated further. However, a smoothed minimum function is needed when fitting measured behaviour in Section VII. As the exact nature of the smoothing is not considered important, different functions could be used. In this work, the following function has been used, since it only depends on a single parameter :
Iv VME transfer time
Table I shows the measured transfer times in per 32-bit word for two different SBCs and various modules. The additional SBC setup overhead of starting DMA (direct memory access) or block transfers depend on how many, , are scheduled at the same time. DMA allows multiple adjacent SiCy requests to be scheduled together on the MVME. The MTDC-32  and MADC-32  are from Mesytec, the V785  and V1190  from CAEN, and the VULOM4b  from GSI and is running the TRLO II firmware .
The time it takes for the basic operation of transferring a -data word essentially determines , , , and . Generally, VME access can be divided into two categories, namely single cycle (SiCy) and block transfer, where the latter can transfer either 32 (BLT) or 64 (MBLT) bits at a time . There is also 2eVME and 2eSST  (both are block transfer modes), but these are not widely supported in front-end modules.
SiCy transfers single data words with minimal overhead. Thus with module producing words, the data transfer time with SiCy reads is
Since the designs of the individual modules also affect the word transfer times, has a module dependence, . While block transfers are asymptotically faster per word (), they may require significant setup times in the SBC:
It is, however, possible to amortize this setup time by performing a so-called chained block
transfer, whereby data is read from multiple modules during the same transfer
With being the number of reads required to determine the amount of data and ensure synchronicity for each module, can be expressed analogous to creftype 10:
So far the discussion has been general. However, to evaluate actual systems, it is necessary to measure the
Table I shows the measured read transfer time for a selection of
commercial modules when read using either
Comparing the MVME and RIO4 SiCy transfer times in Table I, the RIO4 is generally three times faster per word. Note that the timing differences between modules for the same SBC are roughly equal for the two SBCs. This reflects the fact that it is the module VME access handling that determines these differences.
The measurements also clearly show that (M)BLT is significantly faster per word than SiCy, but has a considerable setup overhead.
In Fig. 3 the work performed by the readout loop is sketched as a flow diagram. Generally, the SBC will either poll a register or be notified via an interrupt that a readout should be performed. The trigger logic has then asserted deadtime. When the readout request is found, the SBC will check all module event counters and move the remaining data from all front-end modules to a CPU buffer. Then it can release the deadtime, allowing the front-end modules to acquire more data while the SBC performs any further consistency checks of the acquired data. Afterward, it will resume waiting for the next readout request.
The difference between multi-event and shadow readout is the activities taking place while waiting for a readout request. In the multi-event case, the SBC is mostly idle, except for network transfer tasks.
The shadow readout on the other hand tries to continually transfer data from the front-end modules. This is illustrated for a two-module system in Fig. 4, which also shows the pausing when a module buffer becomes full and the deadtime management.
In the simplest case, the data from each module is transferred to a separate buffer. This avoids potentially fragmenting events, and the collected data can easily be consistency checked. In this fashion, it is no longer needed to limit to the module buffer depth . Instead, the limitation for is the available RAM and the desire to perform regular synchronicity checks. The dependence on is illustrated in Fig. 5, where measured data are shown with point-like markers, and general trends of models are shown as curves. This scheme is used throughout the article. The figure shows for a system which has a conversion time (dashed horizontal line) and produced or words per event with . The figure shows two essential features of the shadow readout: converges towards the limit set by conversion times when is increased. Additionally, only shows a weak dependence on event size with less than variation in when .
The virtual module buffers must eventually be copied to an output buffer. This is done after the consistency check as shown in the flow diagram. However, since a substantial amount of data may have been collected, this can easily take several milliseconds, which may be longer than module buffers can continue to store new events, causing them to assert busy signals. In order to avoid this, each module is assigned two memory buffers operated in a “ping-pong” fashion such that new data is transferred into the currently active buffer. When the modules have been emptied during deadtime, the other buffer becomes active and will be filled with new data. The data from the inactive buffer is copied in chunks interleaved with frequent calls to the shadow readout routine. This is illustrated with the read of the modules in-between the copy blocks in Fig. 4.
We have implemented this readout scheme with a modified version of the readout library nurdlib (formerly known as vmelib) . When the readout polling is performed by the surrounding DAQ framework code, it is necessary to also modify that. The change essentially amounts to one single line of code—a callback routine to allow data transfers in the background while no readout request is detected.
Hardware requirements are the same for multi-event and shadow readout, i.e. there must be an acquisition control module that rejects events whenever deadtime or busy is asserted. This module, which issues the readout requests, must be able to keep track of how many events have been acquired and only request a deadtime-asserting readout after a sufficient number (). In our setup, all these tasks are performed by the TRLO II firmware  running on the GSI VULOM4b module .
To allow the most flexible use of the data from a multi-event readout system, it is necessary also to be able to record for each trigger the detector coincidences that caused the trigger to be selected. This trigger coincidence pattern is recorded for each event by the TRLO II firmware. In order to trust the system, it is also necessary to verify that each trigger has been seen by each module once (none lost, none spurious). This is done by comparing the event counters in the modules regularly, i.e. during each deadtime period. This is enough since a correctly working system would never have mismatches, making any deviation significant. Nurdlib already performs these checks strictly.
Note that shadow readout causes almost continuous activity on the VME backplane during analog conversion. Within our tests, it was no problem, provided that the electronic modules and pre-amplifiers etc. were properly grounded. It is suggested to compare the noise levels with and without shadow readout, e.g. using deadtime-asserting multi-event readout for the latter.
|SBC||Buffer||Network CPU time|
|(Intel x86, 4.5 GHz)||64ki|
Table II shows the CPU time per network write call of bytes for two different SBCs, and a modern server CPU for reference. The values are averages for either a large or a small buffer, the latter typically fitting in low-level CPU cache. The former are representative for DAQ network transfers from large event accumulation buffers.
Vi Single core caveat
Both the MVME and RIO4 have single-core processors, which poses some challenges related to the kernel scheduler of the operating system. The main issue is the conflict between readout and network transfer. The SBC must transfer the data to either an event builder or non-volatile storage, meaning time not spent emptying modules, see Table II. It will, therefore, lower the maximum rate that can be handled. However, before that, it can also impact the livetime of the system, if the network preparation happens in such large uninterrupted chunks that the module buffers become full. This is shown in Fig. 6, where drops by a few percent in the naive case where the network transfer is issued with too large buffers sent to the write system call. The kernel takes too long to complete the request, which causes the drop in . This can be mitigated by breaking the transfer preparation into multiple chunks, each with a call to write directly followed by yielding the timeslot of the network thread (by sched_yield). This allows the readout thread to cycle through the modules for each write. The drop in can be described by considering the maximum time each network preparation chunk should take:
The first term is the average time the module buffer can handle, and the second term the CPU time spent on the readout. The factor accounts for the fact that a Poisson-distributed trigger will sometimes issue a burst of many triggers in an unusually short time interval than the long-term average, and thus fill the buffer more quickly.
The maximum time can, by using the values of Table II, also be expressed as a maximum chunk size, which can be used to control the network processing:
The drop in the livetime ratio as exceeds (as shown in Fig. 6) can be fitted by
We use the “error function” () to describe the slight but measurable drop in around write size .
Using too small chunk sizes, however, will introduce a steep loss, due to the overhead of very many write calls. This is seen for the case in Fig. 6.
The above description has been checked for many combinations of trigger frequencies and event sizes, as presented in Fig. 7. For each case, has been determined from fits of creftype 16 as in Fig. 6 with the value . The curves thus describe estimates of the maximum write size that can be used without affecting performance. At buffer sizes above 64 kiB, the fit assumes that the network overhead is twice as large, matching the measured data. We have however not been able to attribute this effect to a specific cause. The best fit value of corresponds to bursts happening to of times for in the range to . The percentages were obtained from simulations of Poisson-distributed triggers taking a non-extending busy-time into account for stretches of accepted triggers.
Even if the negative impact on the livetime is only a few percent, mitigation is important since the effect is enhanced for multi-node systems as the trigger requests which become blocked on each node are independent. This cumulative effect is illustrated in Fig. 10(b).
Provided that any common data bus between the CPU and the network and VME interfaces can handle the simultaneous traffic, this effect could be mitigated with a multi-core SBC. One core would be dedicated to the readout, while another would handle non-critical tasks such as network transfers.
Vii System characterization
In this section, we will benchmark the shadow readout system versus a regular multi-event readout system using two different sets of modules. Each set is part of actual experiments. The first system was used for the IS633 experiment at ISOLDE (CERN)  and the second one is the current system used at the Aarhus accelerator.
In all cases, the trigger requests are either provided by a CAEN DT5800D detector emulator (pulser) , which can provide a Poisson distributed trigger sequence with a given rate, or by equivalent functionality directly in the trigger logic firmware. The trigger requests are sent to the VULOM4b running the TRLO II firmware, which handles the busy and deadtime logic. It also provides scaler values for the total number of trigger requests and the number of accepted requests.
Throughout the article, measured data are shown with point-like markers, and general trends of models are shown as curves. For illustration, some models are also evaluated for configurations that have not been tested.
Vii-a IS633 system
This is a simple configuration designed to run with very low deadtime. It consists only of an SBC, VULOM4b, Mesytec MADC-32 and Mesytec MTDC-32. In order to achieve high livetime, the MADC is configured in bank toggle mode . In this mode, the MADC toggles between which of its two ADCs that digitize the signals and can thus accept a new event while still processing the previous one. The gate was set to and the module in mode which has a conversion time of . The module will thus only assert busy if three events arrive within a window. However, in practice, pile-up is best avoided, and thus TRLO II emitted a busy after every accepted event.
The modules were configured such that the VULOM4b produced 3 words of data per event, the MADC-32 12, and the MTDC-32 2. The busy was a logical OR between the three modules. The modules could store 170, 481, and 2891 events, respectively. An additional 66 words (mainly scaler values) were produced and read once per readout request.
Fig. 8 shows the livetime ratio as a function of the trigger request frequency when using either the MVME or RIO4. For the MVME, has been measured for multi-event mode using SiCy readout and a buffer depth of 170. The curve through the data points is creftype 1 with . This corresponds to an effective , the expected , and a combined overhead per event of . The green dash-dotted curve shows the expected behavior with zero overhead ( multi-events) and it would only provide a slight improvement since the data transfer dominates the deadtime (curve overlaps with SiCy(170) in the figure). The RIO4 system would perform significantly better with a SiCy readout time per event of only . Fig. 8(b) also shows the curves corresponding to 32- and 64-bit block transfer in the limit of zero overhead per event. Using block transfer, the per-event readout time would be reduced to 4.1 or , respectively.
Fig. 8 also shows the measured for shadow readout doing SiCy reads with a shadow buffer depth of 8192 events. Up to , the data points follow creftype 1 with roughly equal to the gate time. According to the models discussed earlier (creftype 6 together with values from Section IV), the maximum accept frequency the MVME can sustain is while the RIO can handle . Note that up to the respective , the MVME and RIO4 deliver essentially the same livetime performance.
If the maximum bandwidth of SiCy transfers becomes the limiting factor, one could combine block transfer with shadow readout. The red dashed curves labeled Shadow DMA or MBLT in Fig. 8 show such configurations. In this case, the limiting factor is the block transfer overhead, with an expected for the RIO4 with this particular setup and number of channels.
Vii-B Aarhus system
The other system consists of a RIO4, VULOM4b, and six CAEN V785 ADCs. This system is used at the Aarhus University accelerator. To mimic actual production conditions, each ADC module was configured to produce 5 words per event while the VULOM4b produced 3. In total 33 words were produced per event with an additional 66 words produced once per readout.
The CAEN V785 has a 32-entry multi-event buffer and a total conversion time of , which includes settling times etc. Additionally, a gate is used. Hence, the expected deadtime per trigger is . It should also be noted that chained block transfer is not advantageous for the V785, as it only can deliver one event per transfer for these modules. Since we have more events than modules, we will instead model the simultaneous scheduling of 6 block transfers. This has an overhead of , i.e. per event.
In practice, readout with (M)BLT of the CAEN V785 is troublesome with some modern SBCs, since the data length cannot be queried beforehand and instead is marked with a VME BERR* signal. While allowed by the standard, this interacts badly with some SBC block transfer drivers since they do not report the number of actually transferred words, and thus obliterates much of the benefits. In the model, we have assumed that the SBC driver provides the needed information.
Another issue with (M)BLT of the CAEN V785 is that the busy release after conversion is delayed until the ongoing VME transfer has completed . This will inflate the effective conversion time. This effect has also been ignored in the model.
Fig. 9 shows the results obtained for the shadow readout and the measured and estimated behavior of various multi-event modes. The SiCy data transfer time per event is , while BLT and MBLT take and , respectively. This includes the block transfer overhead of compared to the transfer time. However, even in the limit of zero overhead, block transfer does not converge to the limit of conversion and gate time. On the other hand, the data obtained show that SiCy shadow readout can maintain the limit and keep up with the data rate until , and to when scaler readout for every 32nd event is included.
Vii-C Network impact
The above measurements were done without network transport, in order to simplify the system descriptions. The data rates, at a few MB/s, do not use any significant CPU resources for network processing. This is seen in Fig. 10(a) for a single-crate system with and without network transport, where the network overhead due to sending in chunks should use CPU time according to Table II. The lowering of from to corresponds to .
Vii-D Multi-crate system
The shadow readout mode can also be applied to multi-crate systems. The Aarhus system described above (RIO4, VULOM4b, and six CAEN ADCs) was duplicated in a second crate, and is operated together with the first in a master-slave configuration. The data from both systems are sent to an event builder PC for merging. The master start signal is used to generate gates for the modules in both crates for each trigger. The master crate generates the readout triggers, and by means of a TRIVA  mimic connection  they are distributed to be handled simultaneously by the slave system. The readout deadtime is the logical OR combination of the deadtime in the two systems. The busy signals are handled similarly, i.e. busy reported by any module in the total system inhibits further triggers.
The upper plot in Fig. 10 shows that the trigger and shadow readout operation is virtually unaffected by the second crate provided that the execution time of each network write call is limited. The lower plot shows how stalls due to too long network processing that happen at independent events cause losses that scale with the number of involved readout nodes.
Vii-E Multi-crate event correlations
In any multi-event readout scheme, event mixing is a potential cause of severe data corruption, which can look deceptively correct. By having taken multi-event to the extreme, shadow readout is particularly exposed to this. Multi-crate systems naturally also have more vulnerable components.
To show that the regular synchronisation and event counter checks are effective against unintentional event-mixing due to spurious triggers also in shadow readout multi-crate systems, a two-crate system, each with one TDC (CAEN V775), was set up. The TDCs are as usual given the same start signal, and one channel in each TDC is fed the same stop signal, which should give a 1:1 correlation graph for corresponding events, see Fig. 11(a). The stop signal is generated from the start with a random delay of to .
To inject errors, spurious triggers are injected with about in the slave system and its TDC. This introduces additional events from the slave TDC, which cause following events to be erroneously combined between the two systems, until the next synchronization check.
Potentially bad events are separated from the presumed good ones during analysis by the detection of event counter mismatches between the master and slave systems. This is seen in Fig. 11(a), where no mixed correlations are observed among the presumed good events. The bad events still have a pronounced diagonal, since only events in a readout block after the spurious trigger are affected, while the detection granularity is entire readout blocks.
Viii Conclusion and outlook
Three principle ways to operate VME-based readout systems for multi-event capable digital acquisition modules have been described. These schemes are single-event, multi-event, and shadow readout. The necessary considerations to describe the performance of these schemes in terms of total system deadtime, based on the timing of individual operations, have been detailed. From these considerations, it is expected that the deadtime ratio for a scheme in which data readout is performed asynchronously to the conversion should converge to the limit of the busy time of the front-end electronics. An implementation of such a scheme was then presented in some detail, and it was shown that the deadtime ratio converges as long as the VME bus has sufficient bandwidth for the total data rate, using either single-cycle access or block transfer. Finally, a benchmark of two different systems with shadow readout was shown. In both cases, the shadow readout scheme achieved higher livetime than the alternative readout schemes, even when the latter used faster block transfer modes.
At the time of writing, a shadow readout system has been running for several months at the Aarhus University accelerator without problems, and the methods have been successfully used for the IS633 and IS616 experiments at CERN ISOLDE.
The authors would like to extend their thanks to Dr. N. Kurz for the work to provide a stable Linux environment with block transfer modes for the RIO4 SBC. The authors would like to extend their thanks to the Daresbury NPG for providing the MVME Linux environment.
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- J. Hoffmann, N. Kurz, and M. Richter, TRIVA, VME Trigger Module, User Manual, GSI, Darmstadt, Germany, 2007.