# Tunnel Field-Effect Transistors in 2D Transition Metal Dichalcogenide Materials

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## I Abstract

In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the subthreshold swing and energy-delay of these TFETs are compared with conventional CMOS devices.

## Ii Introduction

Power consumption is one of the main challenges for future electronics. In this regard, tunnel FETs are among the most promising candidates for future integrated circuits (ICs) due to their small subthreshold swing (SS) and low OFF-current [1, 2]. Having small SS and OFF-current reduces both static and dynamic power consumption of the ICs [3].

One of the major drawbacks of tunnel FETs is their low ON-current. The current in TFETs is the result of band-to-band tunneling (BTBT) of the carriers. The tunneling probability is usually much smaller than 1 and as a result the ON-currents of TFETs are much smaller than those of conventional FETs. However, the tunneling probability can increase significantly if the electric field at the tunneling region is high enough. Atomically thin 2D devices are very interesting in this context for TFET applications, analogous to nanotubes [1, 2], due to the tight gate control over the channel which results in high electric fields at the tunnel junction. Since the BTBT transmission probability depends on the electric field exponentially, high ON-currents are expected in 2D TFETs. However, tight gate control is not the only player in determining ON-currents and there are other critical factors, such as band gap, effective mass (m), and doping concentration.

The well known scaling length theory [6] can be used to quantify the effect of gate control on the electric field at the tunnel junction [7]. This theory provides a simple analytic way to understand how various device parameters affect the spatial variation of the potential along the channel [6] described by a modified 1D Poisson equation,

(1) |

where and are the electrostatic potential and the natural scaling/decay length of the potential, respectively. In double gated FETs, is given by [8]

(2) |

where , and are the dielectric constants of channel and oxide respectively, while , and are their thicknesses. According to equation (2), reducing the channel thickness reduces the natural scaling length of the potential which results in higher electric fields and ON-currents.

Besides advantageous 2D electrostatics, there are other incentives for using 2D materials for future electronics [9]. For example, thinning the 3D material based FETs (which is required in transistor scaling) increases the effect of surface roughness on carrier transport which leads to lower mobility [10]. However, 2D materials have relatively weak inter-layer bonds and can be exfoliated easily without surface roughness [11, 12, 16, 17]. Moreover, there are no dangling bonds in 2D TMDs unlike thinned 3D materials [13, 14, 15]. Another advantage of 2D materials is that thinning the material does not increase the band gap of the material as much as it does in 3D materials [18, 16]. This is again due to the weaker coupling between stacked layers in 2D materials. For example, thinning InAs nanowires to achieve better gate control can increase the band gap more than 100% [19], while the increase in band gap from bulk to monolayer is much smaller in 2D materials [18]. This is useful in the TFETs as a larger badgap results in a lower ON-current. Moreover, mono-layer 2D materials usually have small dielectric constants [20], which can also increase the ON-current and reduce the drain induced barrier lowering (DIBL) in TFETs.

Previously, TMD TFETs have been simulated without solving the Poisson and the transport equations self-consistently [4, 5]. In these works, the electric field at the source-channel junction has been approximated assuming that the 1D Poisson equation (equation (1)) is accurate throughout the entire source-to-channel junction. Although is a critical factor in determining the electric field, it is not the only factor. Other factors such as the depletion width in the source region are important too. The non self-consistent results predict very large ON-currents for all TMD TFETs irrespective of the channel material. In this paper, the correctness of these assumptions for TMD TFETs has been investigated by solving the 3D Poisson equation self-consistently with full band quantum transport, and the factors limiting the ON-currents are elucidated.

The band structure and electronic properties such as band gap, m, and dielectric constant of TMD materials depend on the number of layers. Consequently, devices with different number of layers show different characteristics. Although increasing the thickness reduces the band gap, it increases and decreases the electric field at the source-to-channel junction. Moreover, multi-layer TMDs usually exhibit indirect band gaps which implies that phonons need to be involved in the BTBT process. As a result, it is favorable to use mono-layer TMDs and instead explore different materials to obtain small values of , direct band gap, and m simultaneously. Since TMDs form a general class of materials of the form MX, where M is a transition metal (Mo, W, etc.) and X is a Chalcogenide (Te, Se, S), a variety of material parameters can be accessed by the correct choice of material. The field of 2D materials is still at its infancy as novel materials are being discovered [23, 24], which opens up opportunities for TFET designs. Accordingly, in this paper, only mono-layers of a set of more common TMDs, whose critical parameters span the design space of TFETs, are studied.

## Iii Simulation method

The TMD Hamiltonian is represented by an spd 2nd nearest neighbor tight-binding (TB) model with spin-orbit interaction. The Slater-Koster TB [25] parameters are optimized based on first principles bandstructures obtained from density functional theory (DFT) with the generalized gradient approximation (GGA). DFT-GGA has been shown to provide band gaps and effective masses in TMDs comparable to experimental measurements [26]. The motivation for using a DFT guided TB model is that a realistically extended device size can be simulated at ease compared to computationally expensive and size limited ab-initio methods [27]. Bandgaps and effective masses of mono-layer MoS, WSe, MoTe, and WTe obtained from our TB model are listed in table I. The TB parameters are general and capture the bandstructure of both bulk and monolayer TMDs. As an example, the TB bandstructure of monolayer WTe is shown in Fig. 1.

In this work, self-consistent Poisson-QTBM (Quantum Transmitting Boundary Method [28]) methodology has been used within the tight binding description. The QTBM method is equivalent to the well known non-equilibrium Green’s function (NEGF) approach without scattering, but is a more computationally efficient implementation [29]. In this method, the Schroedinger equation with open boundaries is solved using the following equation

(3) |

where , , , and are energy, identity matrix, device Hamiltonian, and total self energy due to open boundaries and and are the wave function and a career injection term from either source (subscript S) or drain (subscript D) [29]. The electron and hole carrier density and current can be obtained from the wave function [29]. Since in-plane and out-of-plane dielectric constants ( and ) of TMD materials are different, the Poisson equation reads as follows if considering the z direction to be along the out-of-plane direction (or c-axis) of the TMDs

(4) |

where and are the electrostatic potential and total charge, respectively. The dielectric constant values ( and ) for TMD materials are taken from ab-initio studies [20], [21] and are listed in table I. In this work, transport simulations have been performed with the nanodevice simulation tool NEMO5 [30, 31].

Parameters | MoS | WSe | MoTe | WTe |
---|---|---|---|---|

Eg [eV] | 1.68 | 1.56 | 1.085 | 0.75 |

[m] | 0.52 | 0.36 | 0.57 | 0.37 |

[m] | 0.64 | 0.5 | 0.75 | 0.3 |

4.2 | 4.5 | 8 | 5.7 | |

2.8 | 2.9 | 4.4 | 3.3 |

## Iv Results and discussion

All simulated TMD TFET devices assume a structure as shown in Fig. 2, and have channel and source/drain lengths of 15nm and 10nm, respectively. A doping level of 1e20 cm is assumed in the source and drain regions which seems feasible by molecular doping of source and drain contact regions [32]. A source-drain voltage V of 0.5V is used unless mentioned otherwise. Equivalent oxide thickness (EOT) of top and bottom oxides is set to 0.43 nm to be consistent with International Technology Roadmap for Semiconductors (ITRS) projections for 2027 [33].

### Iv-a Transfer characteristics of TMD TFETs

Fig. 3 shows the transfer characteristics of the TMD TFETs with OFF-current fixed to 1 at 0 gate voltage. It is worthwhile to notice that in TFETs lower OFF-currents can be readily achieved without losing too much ON-current. This is because the slope of the curve is very steep in the low current regime. As a result, a much lower OFF-current can be obtained with a very small reduction of . For example, an OFF-current of 0.1 (10 times smaller than before) can be obtained with the ON-current just being approximately 5-10% smaller.

The simulation results show that WTe TFETs can provide highest performance in terms of ON-current and SS in comparison to the other TFETs. Since WTe has the smallest band gap and effective mass compared to the other TMDs, its ON-current is significantly higher. Notice that despite the fact that MoTe has a smaller band gap than WSe, it shows a smaller current. The values of ON-current (the current at ===0.5V), band gap and reduced effective masses () of these TMDs are listed in table II. Although MoS has a high effective mass for tunneling applications, it is ideal for ultra-scaled MOSFET applications where a high effective mass can suppress the source to drain tunneling [34, 35].

Material | Eg | |||||
---|---|---|---|---|---|---|

WTe | 127 | 0.75 | 0.17 | 0.45 | 2.45 | 3.15 |

WSe | 4.6 | 1.56 | 0.21 | 0.41 | 2.5 | 5.2 |

MoTe | 2.3 | 1.08 | 0.32 | 0.5 | 2.7 | 5.8 |

MoS | 0.3 | 1.68 | 0.29 | 0.38 | 2.5 | 6.3 |

To understand the origin of the difference between ON-currents of these devices, one needs to consider several factors: electron and hole effective masses, band gap, body thickness, EOT of oxide, source-to-channel potential difference, source and drain doping level. These factors are considered in the analytic equation for the current in the ON-state of a TFET [36]:

(5) |

where , , and are the charge of an electron, the reduced Plank constant, and the reduced effective mass, respectively. E is the electric field at the source-channel junction and can be approximated by , where is the effective natural scaling length of the potential at the source-channel junction and is the source-channel potential difference. At threshold voltage, equals . For small overdrive voltages , the current can be simplified using to

(6) |

This equation shows the fundamental factor in determining the current in TFETs is

(7) |

The factor depends on the device design (EOT, body thickness, and doping) through and band structure of channel through and . Note that for small overdrive voltages, the band gap and the effective mass have an equal impact on the current. For example, despite the fact that MoTe has a smaller band gap compared with WSe, it has a larger reduced effective mass which can partly compensate for the reduction in the band gap.

The parameter is composed of two components: the depletion width in the source region () and the natural scaling length () in the gated region. The difference between this analysis and previous works [4, 5, 37] is that the effective natural scaling length is calculated from a self-consistent potential profile which includes the effect of both and accurately. Ideally, the dielectric constant of the channel should be small to make as small as possible. and depend on the in-plane and out-of-plane dielectric constants, respectively. The difference between the values of and , listed in table II, shows the importance of . According to DFT simulations, MoTe has the higher dielectric constant if compared to WSe [20] which further lowers its ON-current. The factor for these materials is shown in table II. The larger the , the smaller the current. By comparing the values, it can be seen that WSe provides higher currents close to the threshold voltage compared to MoTe TFETs in spite of its higher bandgap. Moreover, it is expected that WTe TFET produces the highest ON-current. Note that by employing equation (6), the ON-current ratios between TMD FETs from different materials can be reproduced within reasonable accuracy when using the values from table II.

From Fig. 3, one can conclude that WTe TFETs show promising ON-currents and a steep SS compared to other TMD TFETs. It is possible to further increase the ON-current of WTe TFET by increasing the doping concentration at the source and drain regions. Increasing the doping decreases the depletion width of the source-to-channel interface, which also decreases according to equation (7). Consequently, the ON-current increases. Fig. 3(a) shows a comparison between the ON-currents of WTe TFETs with source/drain doping levels of 1e20 cm and 2e20 cm. In the case of 2e20 cm doping level, the ON-current increases to 350 which is a very high ON-current if compared with other TFETs. It is important to notice that the electric field at the source-to-channel interface depends on both the natural scaling length and the depletion width . As a result, reduction of is not sufficient for high ON-currents. A smaller is also needed. In this regard, the doping of the source and drain region should be designed carefully, whether this doping is chemically or electrically induced. Fig. 3(b) shows the band profiles for these two different doping concentrations. It is apparent that the higher doping concentration shows higher electric field due to the smaller . Notice that the drain region is usually doped less than the source region to suppress the p-branch in the I-V characteristics and improve the OFF-state performance of the TFET [39]. However, due to a relatively large band gap and effective mass of TMD materials, the minimum achievable current in TMD TFETs is always very small and below 1 even for a drain doping level of 2e20 cm. Consequently, lowering the drain doping does not have any significant impact on the transfer characteristics of TMD TFETs.

### Iv-B C-V and DIBL

Fig. 5 shows the total gate capacitance versus the gate voltage (C-V) for the TMD TFETs under investigation. There are two major factors which determine the C-V characteristics: the quantum capacitance, and the threshold voltage. The total gate capacitance (C) can be modeled as a series of oxide capacitance (C), and quantum capacitance (C). The quantum capacitance is proportional to the density of states and m of the material [40, 41]. Materials with larger m have larger C which translates into larger C. On the other hand, the threshold voltage determines the voltage where the charge starts to appear in the channel. Since the off-currents of TFETs have been fixed here, the threshold voltage of one material is different from the other. Clearly, WTe is showing the lowest C values, another benefit when it comes to benchmarking of various TMD devices as discussed below.

Drain induced barrier lowering (DIBL) is one of the most important short-channel effects for ultra-scaled transistors. DIBL causes a reduction of the threshold voltage by the drain voltage, and it is one of the commonly used criteria for indicating short-channel behavior [38]. In TFETs, the active region in which tunneling occurs is right at the source-to-channel interface, far from the drain contact. Moreover, in 2D TFETs, gate control is stronger due to a thin channel which suppresses short channel effects. Consequently, short channel effects are less significant in comparison with conventional FETs (n-i-n or p-i-p doped transistors). The numerical values of DIBL for TMD TFETs obtained in this work are listed in table III. Note that DIBL values of WSe and WTe TFETs are substantially smaller than the reported 80 mV/V DIBL of ultra-scaled MOSFETs [33, 42]. DIBL is calculated at the current level of 1 from the change in the threshold voltage caused by varying V from 0.1V to 0.5V.

(8) |

Among these TMD TFETs, WSe and WTe show a smaller DIBL compared to MoTe. This is because WSe and WTe have a smaller in-plane dielectric constant compared to MoTe which reduces the electric field penetration from drain, and hence suppresses short channel effects.

Material | WTe | WSe | MoTe |
---|---|---|---|

DIBL [mV/V] | 25 | 20 | 67 |

### Iv-C Subthreshold swing and energy-delay product

The main idea behind a TFET is to achieve a steep subthreshold swing below the Boltzmann limit of 60 mV/dec. It is important to compare the steep devices in a generic way. For example, the average subthreshold swing does not provide information about the current range in which the I-V is steep. Recently, a method for benchmarking steep devices has been proposed which gives insight into the local steepness of the I-V curve [43]. In this method, the subthreshold swing is plotted against the drain-to-source current density of the device. Fig. 5(a) shows how mono-layer TMD TFETs fit in this picture. Notice that the current on the horizontal axis is not the ON-current but the current where the SS has been calculated. The devices with the best performance will ideally be placed on the lower right corner of the figure, where the SS is small and the drain-to-source current is large.

Fig. 5(a) shows again that mono-layer WTe is the most promising candidate for TFET applications among the TMD materials considered in this study. Fig. 5(b) shows the energy () versus the intrinsic delay () of a WTe TFET versus ultra-scaled silicon MOSFETs. The WTe TFET shows a smaller intrinsic energy-delay product value when compared to MOSFETs with the same channel length. In terms of the anticipated circuit performance of a 32-bit adder based on TMD TFETs, the performance specs discussed in this article for WTe devices for =0.5V result in the similar energy-delay product as reported by Nikonov et al. [44] for =0.25V. The actual energy and delay values were calculated to be 13fJ and 2450ps respectively using the same code as in [44].

## V Conclusion

In this work, the performance of various Transition Metal Dichalcogenide materials (MoS, WSe, MoTe, and WTe) TFETs has been investigated through self-consistent atomistic simulations. It has been shown that an atomically thin channel alone is not sufficient for high performance TFETs; especially to achieve high ON-currents, the choice of channel material and device design are critical as well. According to our analysis, WTe is the most promising TMD in this study for TFET applications with high ON-currents of 350 . TMD TFETs exhibit reduced short channel effects: DIBL and SS values are significantly lower than for Si MOSFETs (by a factor of about 1/3). Moreover, the energy-delay product of the optimized WTe TFET is lower than that of an ultra-scaled Si MOSFET. Our simulations show that 2D materials with lower band gaps (0.5-0.7eV) and effective masses are more suitable for high performance TFETs.

## Acknowledgment

Authors would like to thank Joe Nahas and Robert Perricone for the 32 bit adder energy-delay calculations and Tarek Ameen for his help with the simulations. This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA. The use of nanoHUB.org computational resources operated by the Network for Computational Nanotechnology funded by the US National Science Foundation under grant EEC-1227110, EEC-0228390, EEC-0634750, OCI-0438246, and OCI-0721680 is gratefully acknowledged.

## References

- [1] J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, Band-to-band tunneling in carbon nanotube field-effect transistors, Physical Review Letters 93, 196805 (2004).
- [2] J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, Comparing carbon nanotube transistors - The ideal choice: A novel tunneling device design, IEEE Transactions on Electron Devices 52, 2568-2576 (2005).
- [3] A. M. Ionescu and H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches, Nature 479, 329â337 (2011).
- [4] R. K. Ghosh et al., Monolayer transition metal dichalcogenide channel-based tunnel transistor, IEEE Journal of the electron devices society 1, 175-180 (2013).
- [5] X.-W. Jiang et al., Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides, Appl. Phys. Lett. 104, 193510 (2014).
- [6] R.-H. Yan, A. Ourmazd, and K. F. Lee, Scaling the Si MOSFET: from bulk to SOI to bulk, IEEE Trans. Electron Devices 39, 1704â1710, (1992).
- [7] L. Liu et al. Scaling length theory of double-gate interband tunnel field-effect transistors, IEEE Transactions on Electron Devices 59.4, 902-908 (2012).
- [8] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, Scaling theory of double-gate SOI MOSFET’s, IEEE Trans. Electron Devices 40, 2326-2329 (1993).
- [9] D. Jena, Tunneling transistors based on graphene and 2-D crystals, Proc. IEEE 101, 1585-1602 (2013).
- [10] T. Low, M.-F. Li, G. Samudra , Y.-C. Yeo , C. Zhu , A. Chin and D.-L. Kwong, Modeling study of the impact of surface roughness on silicon and germanium UTB MOSFET, IEEE Trans. Electron Devices 52, 11, 2430-2439 (2005).
- [11] L. F. Mattheiss, Band structures of transition-metal-dichalcogenide layer compounds, Physical Review B 8.8, 3719 (1973).
- [12] M. Chhowalla et al., The chemistry of two-dimensional layered transition metal dichalcogenide nanosheets, Nature chemistry 5.4 263 (2013).
- [13] Q. H. Wang et al., Electronics and optoelectronics of two-dimensional transition metal dichalcogenides Nature nanotechnology 7.11, 699 (2012).
- [14] J. Kang et al., Graphene and beyond-graphene 2D crystals for next-generation green electronics SPIE Defense+ Security. International Society for Optics and Photonics, (2014).
- [15] S. Vishwanath et al., Atomic Structure of Thin MoSe2 Films Grown by Molecular Beam Epitaxy Microscopy and Microanalysis 20.S3, 164 (2014).
- [16] K. F. Mak et al., Atomically thin MoS2: a new direct-gap semiconductor, Physical Review Letters 105.13, 136805 (2010).
- [17] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis, Single-layer MoS2 transistors, Nature Nanotechnology 6, 147â150 (2011).
- [18] K. F. Mak et al., Atomically thin MoS2: a new direct-gap semiconductor, Phys. Rev. Lett. 105, 136805 (2010).
- [19] C. L. dos Santos et al., Diameter dependence of mechanical, electronic, and structural properties of InAs and InP nanowires: A first-principles study, Phys. Rev. B 81, 075408 (2010).
- [20] A. Kumar and P. K. Ahluwali, Tunable dielectric response of transition metals dichalcogenides MX2 (M=Mo, W; X=S, Se, Te): Effect of quantum confinement, Physica B 407, 4627â4634 (2012).
- [21] T. Cheiwchanchamnangij et al., Quasiparticle band structure calculation of monolayer, bilayer, and bulk MoS2, Physical Review B 85.20, 205302 (2012).
- [22] E. S. Kadantsev and P. Hawrylak, Electronic structure of a single MoS2 monolayer, Solid State Commun. 152, 909-913 (2012).
- [23] H. Liu et al., Phosphorene: An Unexplored 2D Semiconductor with a High Hole Mobility, ACS Nano 8, 4033â4041 (2014).
- [24] P. Vogt et al., Silicene: compelling experimental evidence for graphenelike two-dimensional silicon, Phys. Rev. Lett. 108, 155501 (2012).
- [25] J. C. Slater and G. F. Koster, Simplified LCAO Method for the Periodic Potential Problem, Phys. Rev. 94, 1498 (1954).
- [26] C. Gong, H. Zhang, W. Wang, L. Colombo, R. M. Wallace, and K. Cho, Band alignment of two-dimensional transition metal dichalcogenides: application in tunnel field effect transistors, Appl. Phys. Lett. 103, 053513 (2013).
- [27] Y. Tan et al., Empirical tight binding parameters for GaAs and MgO with explicit basis through DFT mapping, Journal of Computational Electronics 12, 56-60 (2013).
- [28] C. S. Lent, and D. J. Kirkner, The quantum transmitting boundary method, Journal of Applied Physics 67, 6353-6359 (1990).
- [29] M. Luisier , A. Shenk , W. Fichtner and G. Klimeck, Atomistic simulations of nanowires in the sp3d5s* tight-binding formalism: From boundary conditions to strain calculations, Phys. Rev. B, Condens. Matter 74, 20, 205323 (2006).
- [30] S. Steiger et al., NEMO5: a parallel multiscale nanoelectronics modeling tool, IEEE Transactions On Nanotechnology 10, 6, 1464- 1474 (2011).
- [31] J. E. Fonseca et al., Efficient and realistic device modeling from atomic detail to the nanoscale, Journal of Computational Electronics 12, 592-600 (2013).
- [32] Doping levels larger than 2e19 cm have been achieved by molecular doping in TMDs. For example see: L. Yang et al., Chloride Molecular Doping Technique on 2D Materials: WS2 and MoS2, Nano letters 14.11, 6275-6280 (2014).
- [33] Publications of international technology roadmap for semiconductors (ITRS), 2013 editions. (http://www.itrs.net)
- [34] M. Salmani-Jelodar, S. Mehrotra, H. Ilatikhameneh, and G. Klimeck, Design Guidelines for Sub-12 nm Nanowire MOSFETs, IEEE Transactions on Nanotechnology, 14.2, 210-213 (2015).
- [35] K. Alam, and R. K. Lake, Monolayer MoS2 Transistors Beyond the Technology Road Map, IEEE Transactions on Electron Devices, 59.12, 3250 (2012).
- [36] A. C. Seabaugh and Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic, Proc. IEEE 98, 2095-2110 (2010).
- [37] S. Das, A. Prakash, R. Salazar, and J. Appenzeller, Towards low power electronics: Tunneling phenomena in TMDs, ACS Nano 8, 2, 1681â1689 (2014).
- [38] W. Zhaoa et al. , Origin of indirect optical transitions in few-Layer MoS2, WS2, and WSe2, Nano Lett., 13, 11, 5627â5634, (2013).
- [39] V. Vijayvargiya et al., Effect of Drain Doping Profile on Double Gate Tunnel Field Effect Transistor and its Influence on Device RF Performance IEEE Transactions on Nanotechnology, 13.5, 974 (2014).
- [40] S. Luryi, Quantum capacitance devices, Appl. Phys. Lett. 52, 501-503 (1988).
- [41] Z. Chen and J. Appenzeller, Mobility extraction and quantumcapacitance impact in high performance graphene field-effect transistor devices, Proc. IEEE IEDM, 509-512 (2008).
- [42] M. Salmani-Jelodar et al., Transistor roadmap projection using predictive full-band atomistic modeling, Appl. Phys. Lett. 105, 083508 (2014).
- [43] H. Lu and A. Seabaugh, Tunnel field-effect transistors: State-of-the-art, IEEE J. Electron Devices Soc., 2, 4, 44-49 (2014).
- [44] D. E. Nikonov, and I. A. Young, Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (to be published).