Single-User mmWave Massive MIMO: SVD-based ADC Bit Allocation and Combiner Design
In this paper, we propose a Singular-Value-Decomposition-based variable-resolution Analog to Digital Converter (ADC) bit allocation design for a single-user Millimeter wave massive Multiple-Input Multiple-Output receiver. We derive the optimality condition for bit allocation under a power constraint. This condition ensures optimal receiver performance in the Mean Squared Error (MSE) sense. We derive the MSE expression and show that it approaches the Cramer-Rao Lower Bound (CRLB). The CRLB is seen to be a function of the analog combiner, the digital combiner, and the bit allocation matrix. We attempt to minimize the CRLB with respect to the bit allocation matrix by making suitable assumptions regarding the structure of the combiners. In doing so, the bit allocation design reduces to a set of simple inequalities consisting of ADC bits, channel singular values and covariance of the quantization noise along each RF path. This results in a simple and computationally efficient bit allocation algorithm. Using simulations, we show that the MSE performance of our proposed bit allocation is very close to that of the Full Search (FS) bit allocation. We also show that the computational complexity of our proposed method has an order of magnitude improvement compared to FS and Genetic Algorithm based bit allocation of .
Hybrid precoding and combining is a common architecture used with Millimeter wave (mmWave) Massive Multiple-Input Multiple-Output (MIMO) transceivers [2, 3, 4]. Also, in mmWave massive MIMO receivers, low-resolution combining is a popular technique to deal with large power demands by the Analog to Digital Converters (ADC) [3, 4, 5]. In this paper, we propose to combine the SVD-based combining with low-resolution ADCs at the receiver.
In an earlier work, it was shown that for certain channel conditions, the optimal bit allocation across the RF paths is non-uniform and channel-dependent . Hence, we use a generic structure to allow non-uniform bit allocation. Our focus in this work is primarily on the design of ADC bit allocation at the receiver and hybrid combiners via channel SVD. We assume that the hybrid precoder design is independent of combiners and ensure that the optimal hybrid precoders match the right singular matrix of the MIMO channel [4, 6].
We derive the expression for the MSE of the received, quantized, and combined vector. Our contributions in this paper are: (1) we derive the expression for CRLB and show that the MSE achieves CRLB, and (2) we attempt to minimize the CRLB with respect to the bit allocation matrix. The bit-allocation matrix enable variable bit-allocation on the receivers RF-paths. In doing so, we arrive at the conditions for hybrid combiners and a simple algorithm for bit allocation with order of magnitude reduction in computational complexity. We present the simulation results by computing MSE at various SNRs using the proposed bit allocation and Full Search (FS) technique. We simulate the mmWave channel using the simulator of Shu Sun et. al  with 8 and 12 RF Paths. We use 64 Rx and 32 Tx antenna elements arranged in a Uniform Linear Array (ULA).
Ii Signal Model
The signal model for a typical single-user mmWave Massive MIMO transceiver encompassing a hybrid precoding and combining is shown in Figure 1. Here, we denote and to be the digital and analog precoders, respectively. Similarly, we represent and to be the digital and analog combiners, respectively. The vector is an transmitted signal vector whose average power is unity. Let and denote the number of RF Chains at the transmitter and receiver, respectively. Also, and represent the number of transmit and receive antennas, respectively. The channel matrix is an matrix representing the line of sight mmWave MIMO channel with properties defined in .
The transmitted signal and the received signal are represented as
Here, is an noise vector of independent and identically distributed (i.i.d) complex Gaussian random variables such that . The received symbol vector is analog-combined with to get and later digitized using a variable-bit quantizer to produce . This signal is later combined using the digital combiner to produce the output signal . The quantizer is modeled as an Additive Quantization Noise Model (AQNM) [9, 10]. However, when we extend this model to allocate unequal ADC bits (1-4) across RF paths, the AQNM model can be written as [1, 11]. Vector is the additive quantization noise which is uncorrelated with and has a Gaussian distribution: [9, 10, 11].
Hence, the relationship between the transmitted signal vector and the received symbol vector at the receiver is given by
The dimensions of matrices indicated in Figure 1 are as follows:
, , , , and .
We have as the diagonal bit allocation matrix. We intend to design the precoders and , and Combiners and , along with the ADC bit allocation for a given channel realization . We assume that we have perfect CSI at the transmitter. We further assume that the number of RF paths on the receiver is the same as the number of parallel data streams , i.e., . The analysis is easy to extend and similar for the case .
Ii-a Precoder Design
The hybrid precoding and combing techniques for systems employing phase shifters in mmWave transceiver architectures impose some constraints on them. The constraint is to have unit norm entries in the analog precoders and combiners, that is and , respectively. Given the number of constraints we have on the designing these matrices; solving them is quite complicated. Hence, we propose to design the precoder and combiner separately. For the precoder design, we employ the technique used in [4, 6]. Let the SVD of the channel matrix be
The hybrid precoders are derived upon solving the optimization problem  stated below.
The set is the set of all possible analog precoders that correspond to hybrid precoder architecture based on phase shifters. This includes all possible matrices with constant magnitude entries.
Ii-B Combiner and Bit-allocation Design
We now design the combiners such that the MSE of the received, quantized and combined vector is minimized. Having designed the precoders in the previous section such that with the constraints in (4), we can rewrite (2) as
Using (5) we derive the expression for MSE as
The first term of in (7) is channel-dependent, and the only design parameter we have in our control to minimize is to ensure that the second term vanishes. Thus, the combiners and bit allocation matrix needs to be designed with the condition given as:
This is a hard problem to solve for , , and . Thus, we take a slightly different approach. We will prove (theorem 1) that (7) is indeed the Minimum MSE (MMSE) that can be achieved for a given , , , and channel . This is accomplished by deriving the expression for the CRLB for estimating , given the observation . Secondly, we view the CRLB as a function of design parameters , , and , and minimize the CRLB to design them .
We look at the problem in (5) as an Estimation problem, such that we need to estimate given is observed; given that , , are fixed. For simplicity of notation, we will write as . Now, we will rewrite the (5) as
where , and We know that and are Gaussian random vectors, with the following statistics:
The statistical distribution of is given by:
Thus, the statistics of follows:
It is noted that is an matrix with . It is safe to assume that has a full row Rank and its pseudo inverse exists .
Now, on setting , the expression for the CRLB is simplified to
Minimizing the CRLB
Given the fact that the MMSE derived using (7) achieves CRLB for fixed design parameters, we now intend to design the combiners , and bit allocation by minimizing the CRLB . Referring to (16), we wish to have vanish or gets close to zero:
Substituting into (18) and simplifying the equation, we arrive at
Phase shifters or splitters impose constraints on the design of the analog combiner . We will denote the constrained analog combiner as . The imperfections in the analog combiner are compensated by the digital combiner:
We also would like to design the actual analog combiner and the digital combiner , such that:
The analog and digital combiner can now be designed more easily. We start with , then we adjust the and to meet the necessary constraints.
In order to satisfy (22), the condition for the bit allocation becomes:
Since , and are diagonal matrices, we can rewrite as a set of inequalities:
where is the diagonal element of , is the noise power, is the ratio of the Mean Square Quantization Error (MQSE) and the power of the symbol for a non-uniform MMSE quantizer with bits along the RF path , . The values for are indicated in the Table I. and are the column of the matrix and , respectively.
Ii-C Algorithm Description for bit allocation
We need to satisfy all the inequalities in (24) to attain the optimal bit allocation. However, it would not be possible to attain optimal bit allocation, given the number of bits and the power budget. In such scenarios, we would make a best effort approach to satisfy the set of equations in (24) and the solution would be the best solution given the bits and power constraints.
For a given , we first form a super set of all possible bit allocations  that satisfy the given ADC power budget as
Iii Test Setup and Simulation Results
We simulate the mmWave channel using the NYUSIM channel simulator with the configurations specified in Table II . We strengthen the singular value on the dominant channel to simulate a strong scatterer . With this simulated channel, we use or strong channels (RF paths) to spatially multiplex 64 QAM data symbols.
With the above channel, we run the FS technique to arrive at the optimal bit allocation and compute the MSE . We do this at various SNRs. This simulation is shown in pink for and in Figure 3 and Figure 3, respectively. Similarly, we run the simulation to arrive at the bit allocations using our proposed approach. The simulation of MSE at various SNRs are plotted in black. In both situations, we set the ADC power budget to be the power consumed on having 2-bit ADCs on all RF paths. We constraint the ADC bit resolution between 1 and 4 bits. Figures 3 and 3 also has simulations of MSE performance at various SNRs on having all 2-bit ADCs (red plots), all 1-bit ADCs (blue plots), and no quantization (green plots).
Table III and Table III summarizes the computational complexities of FS, GA and our proposed algorithm. Table III captures the number of evaluations of MSE in (6) required for FS Algorithm and GA, and the number of evaluations of gains in (27) for CRLB-based algorithm to arrive at the solution.
The evaluation of MSE requires computation of in (5) which requires multiple matrix multiplications with signal vector of order in the least. Hence, computational complexity of MSE is . However, the computation of in (27) requires 2 dot product evaluations of size and , times. Hence its computational complexity is . Thus, the CRLB-based bit allocation brings down the computational complexity compared to the FS algorithm and GA by an order of magnitude.
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