A Supplemental Material

Proximity Effect Transfer from NbTi into a Semiconductor Heterostructure via Epitaxial Aluminum


We demonstrate the transfer of the superconducting properties of NbTi—a large-gap high-critical-field superconductor—into an InAs heterostructure via a thin intermediate layer of epitaxial Al. Two device geometries, a Josephson junction and a gate-defined quantum point contact, are used to characterize interface transparency and the two-step proximity effect. In the Josephson junction, multiple Andreev reflection reveal near-unity transparency, with an induced gap and a critical temperature of . Tunneling spectroscopy yields a hard induced gap in the InAs adjacent to the superconductor of with substructure characteristic of both Al and NbTi.

Figure 1: (a) MBE-grown InAs/Al hybrid heterostructure. (b) Illustration of superconductor deposition and patterning. The native Al oxide is removed in the lithographically defined areas by Ar ion milling, leaving behind a ragged top surface of Al. The NbTi superconductor stack is then deposited without breaking vacuum. After liftoff, the NbTi stack serves as an aligned etch mask for an Al wet etch. (c) The NbTi stack includes a Ti layer to promote adhesion and a NbTiN capping to prevent oxidation. (d) False-color electron micrograph of an S-Sm-S device after the Al etch similar to the sample measured. (e) False-color electron micrograph of the finished S-QPC-Sm device.

Intimate coupling between semiconductors (Sm) and superconductors (S) gives rise to novel applications of superconducting electronics Weinstock and Raslton (1993), as well as superconducting qubits Clarke and Wilhelm (2004) and new topological states of matter Alicea et al. (2011); Leijnse and Flensberg (2011). A critical building block for S/Sm hybrids system is a transparent interface, ensuring high probability of Andreev reflection Blonder et al. (1982); Octavio et al. (1983). However, obtaining a transparent S/Sm interface has been a technological challenge for decades Amado et al. (2013); Wan et al. (2015); Takayanagi and Akazaki (1995). Recent work has largely resolved the interface problem by realizing epitaxial growth of Al on InAs via molecular beam epitaxy (MBE), both for nanowires Chang et al. (2015); Krogstrup et al. (2015) and, more recently, for two-dimensional electron gases (2DEGs) Shabani et al. (2016), which are better suited for realizing complex, branched devices Alicea et al. (2011). Focusing on InAs 2DEGs with epitaxial Al, high interface transparency and a hard induced superconductive gap meV have been measured both by tunneling spectroscopy via a S-quantum point contact (QPC)-Sm junction Kjaergaard et al. (2016) and by analysis of multiple Andreev reflection (MAR) in a S-Sm-S junction Kjaergaard et al. (2016).

Despite its modest superconducting gap, critical temperature and critical magnetic field, Al has been the material of choice for Sm-S epitaxy to date because it is present in conventional III-V MBE systems and is compatible with standard fabrication recipes. In situ deposition (without breaking vacuum) or direct epitaxial growth of larger gap superconductors has proven challenging and requires dedicated growth systems. As an alternative, we demonstrate in this work the transfer of large-gap properties of NbTi via the proximity effect through a thin epitaxial Al layer into an InAs 2DEG.

Starting from an InAs heterostructure with epitaxial Al, we pattern ex situ a NbTi-based superconductive layer using standard lithographic techniques. The NbTi layer enhances the Al gap by the proximity effect Brammertz et al. (2001); Cherkez et al. (2014), which in turn results in an enhanced induced gap in the InAs 2DEG. As the processing only involves the topmost Al surface, the high transparency of the epitaxial InAs/Al interface is not affected. As discussed below, the induced gap in the InAs 2DEG is found to be more than twice as large as both the induced gap using Al alone Kjaergaard et al. (2016, 2016) and the gap of the Al itself. The method can be extended to other choices of top-layer superconductor Brammertz et al. (2001).

We investigate two device geometries, an S-Sm-S Josephson junction and a S-QPC-Sm junction. The S-Sm-S device shows pronounced MAR features, indicating high transparency, and we extract an induced gap,  meV and a critical temperature,  K, with the zero resistance state across the junction persisting up to 3.7 K. Tunnel spectroscopy in the S-QPC-Sm device yields an induced gap of 0.43 meV and a hardness of the induced gap (measured by a sub-gap conductance suppression in the tunnel regime) comparable to the theoretical limit for S/Sm junctions Beenakker (1992). Tunnel spectroscopy in a magnetic field reveals a gap closing at a critical in-plane field value of , a value times larger than in similar systems without NbTi Kjaergaard et al. (2016).

The InAs heterostructure, grown on an undoped GaSb wafer along the [001] crystallographic direction, is shown in Fig. 1(a). The active region is similar to previous studies Shabani et al. (2016), but with a nominal epitaxial Al layer, instead of the 10 nm Al layer used previously. Thicker Al allowed this layer to be thinned during fabrication without risking etching down to the interface, as discussed below. Transport measurements in a Hall bar with the Al removed were used to extract a mobility of at a density of .

Critical fabrication steps are outlined in Fig. 1b, with full details given in the Supplemental Material Sup (). First, areas for NbTi deposition are patterned using electron-beam lithography. Inside the deposition chamber, the native oxide on Al is removed using Kaufman Ar milling, followed immediately by evaporating Ti and sputtering NbTi/NbTiN without breaking vacuum, as shown in Fig. 1(c). The Ti bottom layer promotes adhesion and the NbTiN top layer prevents subsequent oxidation. Following liftoff, the patterned NbTi forms a self-aligned mask for a selective Al etch. Fabrication steps not shown in Fig. 1(b) include mesa etching, deposition of of by atomic layer deposition, and evaporation of Ti/Au top gates.

Figure 1(d) shows an S-Sm-S device similar to the one measured. The measured device had a separation between the superconducting banks of and a width of 1. Figure 1(e) shows the measured S-QPC-Sm device. All measurements were carried out using standard AC lock-in techniques in a dilution refrigerator with base temperature of . The S-Sm-S device was measured with a current bias; the S-QPC-Sm device was measured with a voltage bias.

Figure 2: Characterization of a S-Sm-S device similar to that shown in Fig. 1(d). (a) Differential resistance as a function of temperature, showing harmonic structures due to MAR resonances. Traces are successively offset by 6 . Peaks in resistance corresponding to different order of MAR resonances are highlighted by symbols: : 2nd, : 3rd, : 4th and : 5th. (b) Critical current (left axis) and zero bias resistance (right axis) as a function of temperature. is extracted from (a) and the zero bias resistance was measured while increasing temperature, here binned in steps of 0.01 K. (c) Differential conductance vs voltage at base temperature showing dips/peaks arising from MAR. 2nd to 5th order MAR are highlighted as in (a). Inset shows how the induced gap, , is extracted from linear fit to the MAR formula . (d) Temperature dependence extracted as shown in the inset of (c), is fitted by Eq. 1 with and as parameters. Colors are used to enable comparison of data between sub-figures.

The induced gap under the superconducting leads Octavio et al. (1983); Flensberg et al. (1988) and the interface transparency Chrestin et al. (1997) can be extracted from MAR measurements in the S-Sm-S junction. As discussed in Ref. Kjaergaard et al. (2016), a characteristic feature of InAs/epitaxial Al Josephson junction is that sub-gap MAR features appear as peaks in resistance rather than in conductance, a consequence of the high S/Sm interface transparency. Differential resistance as a function of DC bias at various temperatures is shown in Fig. 2(a). At base temperature, the critical current, , with normal-state resistance reached at . The product was and critical current density was , both considerably larger than that measured S-Sm-S junctions with epitaxial Al alone Kjaergaard et al. (2016).

As seen in Fig. 2(b) the junction remains in the zero-resistance state up to , above which resistance increases up to a plateau at , which we interpret as the normal-state resistance of the junction. The sharp transition at is associated with the critical temperature of the NbTi contacts. The differential resistance displays pronounced MAR features, appearing as sharp peaks in resistance [or dips in conductance, see Fig. 2(c)].

From the MAR relation , a linear fit of the inverse MAR index as a function of the voltage bias , [Fig. 2(c) inset] yields a base temperature induced gap . Repeating the procedure over a range of temperatures yields , shown in Fig. 2(d) along with a fit to the BCS form Tinkham (1996),


giving and as fit parameters. Experimental data and the BCS fit are in good agreement.

Figure 3: Characterization of the S-QPC-Sm device shown in Fig. 1(e). (a) Differential conductance d/d as a function of the voltage drop across the QPC . Data is measured with the S-QPC-Sm device in the tunnel regime. An induced gap, , is extracted as half the peak-to-peak distance. For comparison the gap of bulk Al is also displayed. (b) Zero-bias conductance, versus an averaged of conductance at high finite bias . Values are extracted from a bias-gate-2D map of conductance, shown in the appendix and are slightly binned. Black curve is a theoretical prediction for perfectly transparent junctions, eq. 2, with no free parameters.

A requirement for the use of S/Sm devices for certain applications, including topological quantum computing, is the absence of sub-gap states, reflected in a small sub-gap conductance. Using the approach of Ref. Chang et al. (2015); Kjaergaard et al. (2016), we measured electron tunneling near the S/Sm interface using a gate-defined QPC fabricated on top of an ALD oxide. A false colored SEM of the device is shown on Fig. 1(e).

Figure 3(a) shows the differential conductance as a function of source-drain bias where the gates are energized to set the QPC in the tunneling regime. In this case, the differential conductance maps the local density of states, allowing the induced gap at the position of the QPC to be directly measured. Defining as the peak to peak separation gives , as shown in Fig. 3(a), similar to the value measured via MAR. In addition to the large energy gap—a factor larger than the Al-only case Kjaergaard et al. (2016))—the hardness of the gap at zero energy is not affected by the additional fabrication. To demonstrate this, we measure similar curves as Fig. 3(a) for different values of out-of-gap conductance, which result in varying in-gap conductance, and produce the parametric plot of Fig. 3b (markers). These data are compared to theory of a single mode S/Sm interface Beenakker (1992),


with no fit parameters.

Here is the conductance in the superconducting regime, is the normal state conductance (measured at high source drain bias) and is the conductance quantum. The agreement is remarkable up to four order of magnitude, demonstrating our devices operate in the theoretical limit of low in-gap conductance. The complete data set is presented in the Supplemental Material Sup ().

Figure 4: Magnetic field dependence of the S-QPC-Sm device of Fig. 1(e). (a) Differential conductance d/d as a function of source-drain voltage and parallel field , perpendicular to the current. Four colored lines show the values of the line cuts in (b). (c) d/d as a function of and out-of-plane field . Four colored lines show the values of the line cuts in (d)

In order to drive the system in the topological regime, a necessary condition is that the Zeeman splitting in InAs, , exceeds while the parent superconductor remains gapped. Previous measurements on InAs/Al heterostructures showed a gap closing at in-plane fields , compatible with , a reasonable value for InAs Kjaergaard et al. (2016). Similar measurements presented in Fig. 4(a,b) indicate a gap closing for in-plane magnetic fields of , consistent with an induced gap times larger than experiments with epitaxial Al. We note that gap closing is not linked to the quenching of superconductivity in the parent superconductor as NbTi can sustain much larger fields than those used here. A different situation is observed when the field is applied out-of-plane, as shown in Fig. 4(c,d). In this case the most prominent effect is not a gap closing (the peaks do not approach zero), but rather a gap softening above that makes the gap indistinguishable from the background. We interpret the softening as due to dephasing of Andreev pairs in the presence of vortices penetrating the S/Sm stack in a large out-of-plane fields Tinkham (1996).

The possibility to locally control the induced gap (and critical field) in the Sm by combining regions with only epitaxial Al or with NbTi/Al stacks allows the realization of complex devices required for future studies of topological states of matter Aasen et al. (2016). For example, NbTi could be used to realize superconductive leads that persist in the trivial regime while one dimensional devices, proximatized by epitaxial Al only, undergo the topological transition.

In summary, we have demonstrated a method for obtaining a S/Sm heterostructure with high interface transparency and a large, controllable induced gap. The processing is based on MBE grown InAs/Al heterostructures and ex-situ deposition of a large-gap superconductor. The technique does not compromise the epitaxial interface and so should be compatible with a variety of materials and processing technologies. Our results suggest a path toward semiconductor-superconductor electronics, both conventional and topological, operating in the temperature range of liquid helium or pulse tube coolers.

We thank S. Upadhyay for useful discussions on fabrication. Research supported by Microsoft Station Q, the Danish National Research Foundation, the Villum Foundation, and the European Commission through a Marie Curie Fellowship.

Appendix A Supplemental Material

This supplemental Material Section describes the experimental procedures used to fabricate the devices presented in the main text and presents additional electrical measurements

Appendix B Fabrication techniques

Here we present detailed information on the fabrication of the reported devices. All patterning was done by e-beam lithography and unless otherwise stated, standard PMMA resist was used. To reduce exposure time, all designs were divided into inner structures with small beam current and outer structures with larger beam current.

To enable alignment of consecutive exposures, alignment marks are made from a Ti/Au (5/100nm) deposition. The marks are placed near the edge, all around the 2.55 mm chip.

b.1 Argon Milling and NbTi deposition

Starting from the blank chip with alignment markers, we spin coat an MMA/CZAR resist bilayer. The choice of this resist stack is particularly important for a successful Ar etching and deposition step. In particular, the bottom MMA layer provides a sizable undercut to facilitate the lift-off of closely spaced contacts while the CZAR layer can sustain prolonged Ar milling times.

Argon Milling is used to remove the native oxide that forms on the epitaxial Al upon exposure to air, allowing the NbTi to directly contact the metallic Al. For this step we used a Kaufman ion source installed in the superconductor deposition chamber. The etching was performed with a beam voltage of 600 V, an acceleration voltage of 120 V, an Ar-flow of 30 sccm at 1 mTorr pressure and with a rotating sample plate. The desired etching depth in the epitaxial Al is between and .

The etching rate of Kaufman source can fluctuate over long periods of time, requiring a fine tuning of the etching time prior to each run. In order to reduce the consumption of epitaxial material, two distinct etching rate calibrations was performed on Si chips with thermally grown SiO layer. We found that etching 24.5 nm of SiO resulted in an optimal etch depth in the epitaxial Al layer. The etching depth was measured with an optical profilometer for epitaxial Al and a spectral reflectometer for SiO. For every etching session, the Kaufman filament was heated by a  minutes milling of an empty sample plate. The sample was subsequently loaded in the deposition chamber and two more minutes of milling were performed on a closed sample shutter before allowing the Ar ions to reach the sample. The samples presented in the Main Text were etched 3 min and 31 sec.

Immediately after Ar etching the superconductive Ti/NbTi/NbTiN stack is deposited in the same chamber. First 2 nm of Ti are e-beam evaporated to ensure good contact between NbTi and Al. Second, 60 nm of NbTi are deposited from a NbTi sputter target with a beam power of 200 W in a 4 mTorr pressure with an Argon flow rate of 50 sccm, resulting in a deposition rate of . When the desired NbTi deposition is terminated, the sample shutter is closed. Third, a N flow of 6 sccm is let into the chamber and the shutter is opened again after 30 sec to deposit 5  nm of NbTiN. The sample is kept rotating during the entire deposition to ensure uniformity.

After deposition, the resist bilayer is lifted-off by immersion of the sample in dioxolane. Sputtering deposition on a undercut resist results in prominent sidewalls, high and narrow structures that can cause several problems during the remaining fabrication steps. Most sidewalls were removed by sonication during liftoff of the sputtered material.

The epitaxial Al wafers do not require specifically designed bonding pads, as low resistance () contacts can generally be obtained by directly bonding on the epitaxial Al. In the present case, however, the epitaxial Al covering the surface (and not protected by NbTi) will be removed in a subsequent step. For this reason it is important to deposit NbTi also on the bonding pads of the mesa structure.

b.2 Mesa Etching and Al etching

A new resist-pattern is defined for mesa etching on standard PMMA. After chemical development with MIBK:IPA 1:3, the chip is plasma ashed for 60 sec to remove possible resist leftovers. The etching is performed in two steps. First the epitaxial Al, that covers the entire surface of the wafer, must be removed. Second, the III/V semiconductor is etched to isolate different devices on the same chip. The epitaxial Al is removed by a 12 sec etching in 50 C Transene Aluminum Etchant type D. The process is terminated first with 30 s stirring in 50 C DI water and then 30 s stirring in room temperature DI water.

After blow drying the chip with nitrogen, the III-V is immediately etched by a prepared room temperature HO:CHO:HPO:HO (220:55:3:3) solution for 330 s, resulting in an etching dept of about 600  nm. The ethcing is stopped with stirring in room temperature DI water. The resist is lifted off with dioxolane, followed by washes in acetone and isopropanol. At this point the NbTi forms a self aligned mask that can be used for etching the epitaxial Al covering the mesas, so no further electron beam lithography step is needed. The Al etching step previously described is then repeated, but with no resist mask.

b.3 Atomic Layer Deposition of HfO and gate deposition

Immediately after removing the unwanted epitaxial Al, the chip is transferred in an atomic layer deposition chamber for the growth of 50 nm HfO as a gate insulator. To minimize the exposure of the uncovered III-V material to oxygen, a constant flow of 20 sccm of N is maintained in the chamber at any stage, also during pumping down. HfO is deposited by 500 cycles of Tetrakis(dimethylamido)hafnium pulse and 60 sec waiting time and water pulse and 60 sec waiting time preheated at 90 C.

Top gate deposition is done in two steps, one for the fine features and the other for larger elements such as bonding pads. In Fig. 1(e) of the Main Text it is possible to distinguish the two depositions from their different metal height and surface roughness. The fine features are defined in a single PMMA layer by evaporation of 5 nm Ti/30 nm Au and lift-off. The larger features are defined in a MMA/PMMA bilayer and require the evaportation of 50 nm Ti/700 nm Au. In both cases the chips are plasma ashed for 60 s after development to remove eventual resist leftovers.

S-Sm-S in-plane field dependence

Figure S.1: In-plane field dependence of the S-Sm-S. (a) Differential resistance as a function of source-drain current and in-plane field , applied perpendicular to the current flow. Colored squares show -values at which line cuts in (b) are taken. These line cuts are not offset.

An in-plane field, perpendicular to the current direction, is applied on the S-Sm-S junction while measuring critical current , see Fig. SS.1. The vector-magnet was aligned before the measurement. Still is fluctuating at low fields, indicating flux jumps. These stabilizes at higher fields until the super-current dies out at 500 mT. The sweeps are taken going from negative to positive, causing heating effects in the negative current region giving rise to the visible asymmetry of .

Appendix C QPC Conductance

Beenakker predicted in 1992 Beenakker (1992) that an Andreev-enhanced QPC, like the one reported in this work, should have steps in conductance after pinch-off. This was observed in an InAs 2DEG with epitaxial Aluminum S-QPC-Sm junction Kjaergaard et al. (2016). Despite the reported S-QPC-Sm does not show clear step features, presumably for the lower electron mobility of the wafer used in this work, the first plateau fluctuates around rather than , see figure. SS.2.

Figure S.2: Differential conductance as a function of gate voltage , at zero bias, close to the pinch-off of the QPC.

c.1 Conductance in the tunneling regime

The parametric plot presented in Fig. 3(b) of the Main Text shows the QPC zero bias conductance as a function of the QPC high-bias conductance (which coincides with the normal state conductance up to experimental errors). The parametric plot was obtained from the measurement presented in Fig. S.3, showing the QPC conductance as a function of bias and gate voltage close to pinch-off.

To accurately measure the sample conductance in the very low transmission regime, we used DC techniques only in a two-terminal configuration. A line resistance was determined in a four-terminal measurement at . Figure Fig. S.3 is obtained by numerical differentiation of the measured DC current as a function of . The voltage dropping on the QPC was calculated as . The noise visible in Fig. SS.3 is presumably due to a combination of the differentiation method and intrinsic noise of the device, also noticed in AC measurements.

Figure S.3: Numerically differentiated current vs source-drain voltage for gate voltages close to pinch-off with the QPC.


  1. Image is taken before etching, ALD and gate deposition.


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