Phase Noise and Jitter in Digital Electronics

Phase Noise and Jitter in Digital Electronics

Claudio E. Calosso and Enrico Rubiola CEC is with INRIM, Division of Physics Metrology, Torino, Italy. E-mail c.calosso@inrim.itER is with FEMTO-ST Institute, Univ. Bourgogne - Franche Comté, and CNRS. Address: ENSMM, 26 Chemin de l’Epitaphe, 25030 Besançon, France. Home page E-mail
July 12, 2019

This article explains phase noise, jitter, and some slower phenomena in digital integrated circuits, focusing on high-demanding, noise-critical applications. We introduce the concept of phase type and time type (for short, -type and -type) phase noise. The rules for scaling the noise with frequency are chiefly determined by the spectral properties of these two basic types, by the aliasing phenomenon, and by the input and output circuits.

Then, we discuss the parameter extraction from experimental data and we report on the measured phase noise in some selected devices of different node size and complexity. We observed flicker noise between and at 1 Hz offset, and white noise down to in some fortunate cases and using the appropriate tricks.

It turns out that flicker noise is proportional to the reciprocal of the volume of the transistor. This unpleasant conclusion is supported by a gedanken experiment.

Further experiments provide understanding on: (i) the interplay between noise sources in the internal PLL, often present in FPGAs; (ii) the chattering phenomenon, which consists in multiple bouncing at transitions; and (iii) thermal time constants, and their effect on phase wander and on the Allan variance.

Keywords: Phase Noise, Jitter, Aliasing, FPGA, Bouncing, Allan Variance, Thermal Stability.

1 Introduction

Timing analysis is generally driven by the design of logic functions. That is why specs like “the input must be stable 600 ps before the clock edge” are just countless. From this standpoint, it is sufficient to describe the fluctuations in terms of jitter. Broadly speaking, jitter is the time fluctuation, evaluated in reference conditions. Because of the wide bandwidth, jitter is chiefly determined by the white noise. Notice that proper operation requires an analog bandwidth 3–4 times the switching frequency, and in turn up to a few GHz with nowadays components.

When the design comes to spectral analysis and to highly stable oscillators, language and requirements change radically. Fluctuations are generally described in terms of phase noise, expressed either as or , and the low-frequency phenomena are no longer negligible. Low phase noise is crucial in radars [1, 2, 3], modern telecomm [4], atomic frequency standards [5] and particle accelerators [6, 7], just to mention some.

In the rapidly changing world of digital electronics, the literature on phase noise is rather old and focuses on frequency dividers, either in TTL and ECL components [8, 9], or in transistor-level modeling. Other references found are more about data transfer in telecom networks than about components [10, 11, 12].

At the time of [8, 9], CMOS technology was used only in microprocessors and complex functions. Gate arrays and FPGAs came later, with a new rapid progress [13, 14, 15]. Interestingly for us, gate arrays and FPGAs bridge the gap between logical/computational functions and circuit-level design. The precise control on electrical signals that follows opens a new challenge in understanding noise. However, VLSI engineers are mostly concerned with noise margin, crosstalk, and power distribution [16]. Conversely, amplitude and phase noise are not studied.

The purpose of this article is to set the basic knowledge about phase noise, and to provide examples. We focus on the clock distribution because clock edges are the most critical ones for timing. This does not sounds a limitation, first because critical signals can be synchronized to a clock line, and second because a chip in charge of a highly critical operation should not perform multiple tasks ‘cross-talking’ at random with one another.

Designing the experiments was initially difficult. However, after a noise model and the first results were available, reproducing similar experiments is surprisingly simple. We hope that the reader will be able to port our ideas to other technologies and logic families. The reader may also learn about reverse engineering the noise.

2 Definitions, and Phase Noise Models

Noise Type Dependence on Main Equation Derived Equation


Pure phase type

(pure -type)

(12) (13)      

Aliased phase type

(aliased -type)

(10) (11)   

Pure time type

(pure -type)

(15) (16)

Aliased time type

(aliased -type)

(17) (18)
Table 1: Phase Noise Types and Their Parameters

Phase noise is often expressed as the one-sided PSD of the random phase . In technical literature we often find , defined as and given in dBc/Hz [17]. Alternatively, phase noise is represented as the phase time fluctuation , and its PSD . Since is equivalent to converted into time, it holds that


where is the carrier frequency. Our notation is consistent with general literature [17, 18], yet for the choice of fonts for some specific quantities as a minor detail.

A model which is useful to describe phase noise is the polynomial law


where the integer depends on the device. After (2), it holds that . The sum (3) describes the usual noise types: white phase noise , flicker phase noise , white frequency noise , etc. Common sense suggests that in two-port components, noise processes higher than (i.e., , ) cannot extend over unlimitedly low frequencies, otherwise the input-output delay diverges in the long run.

The polynomial law is also used for the PSD of the voltage noise


(notice the font in , because reserved for ). The reader familiar with analog electronics finds an obvious analogy with the parameter [], specified separately for white and flicker noise.

The rms time fluctuation can be calculated integrating over the system bandwidth (Parseval theorem)


The lower limit is set by maximum differential delay in the system. The upper limit is . The reason is that the fluctuations are sampled at the clock edges, thus at . The quantity can be identified with the variance , yet after filtering out the part.

For our purposes, is approximately equivalent to the rms jitter. By contrast, the general term ‘jitter’ has wider scope, mostly oriented to SDH telecomm systems. It includes different types of noise and interferences starting at 10 Hz, with different weight for each (the term ‘wander’ is preferred below 10 Hz). See for example [19, 20, 10] for standards and useful digressions. In a FPGA, there may be a factor 1000 between the rms jitter and the overall jitter, also including interferences.

We introduce two basic types of process discussed below, which take their names from the frequency-scaling properties.

The phase-type (or pure phase-type) process is, by definition, a process in which the statistical properties of are unaffected after changing the carrier frequency in a suitable wide range. Hence, scales with according to (1).

The roles of and are interchanged in the time-type process. So, the time-type (or pure time-type) process is, by definition, a process in which the statistical properties of are unaffected after changing the carrier frequency in a suitable wide range. Of course, scales according to (1).

The concepts of phase-type and time-type process apply to phase noise, wavelet variances (Allan and Allan-like), environmental effects, etc. Most readers are familiar with the ‘personality’ of the -type noise from the phase noise of RF/microwave amplifiers [21]. Thermal noise, flicker, and some environmental effects in amplifiers behave in this way. Conversely, the thermal drift of the delay in a coaxial cable or optical fiber are time-type processes. The -type noise also describes the ideal noise-free synthesizer, which transfers from the input to the output, independently of .

3 Noise in the Clock Distribution

Figure 1: Block diagram describing the noise in the clock distribution.

A lot about phase and time fluctuations can be learned from the simple model sketched in Fig. 1. The input signal of frequency is first converted into a square wave with full voltage swing, full slew rate and full bandwidth, and then distributed. Restricting our attention to white and flicker, we get the four behaviors listed in Table 1 and discussed below.

3.1 Spectrum of the Phase-Type (-type) Phase Noise

In digital circuits we often encounter the aliased -type noise. Let us start with -type noise at the input of a digital circuit, where the input signal crosses a threshold affected by a fluctuation . Under the assumption that the input Slew Rate (SR) is high enough to avoid multiple bouncing (Sec. 6), we get and, after (1),


Notice that the direct measurement of is possible only in simple circuits which allow the simultaneous access to input and output of the gate.

The sinusoid is the preferred clock waveform because it propagates through circuit boards with best impedance matching and lowest crosstalk and radiation, and because high purity reference oscillators work in sinusoidal regime. Discarding the dc component and setting the threshold at 0, the clock signal


has slew rate . In this conditions, the phase fluctuation is


Generally, the analog bandwidth of a digital circuit is greater than the max by a factor of 3–4. This is necessary for the device to switch correctly. In turn, the bandwidth of is equal to . Squaring the input signal samples at the zero crossings introduces aliasing. The spectrum of the sampled signal is


where the and higher terms are neglected because of the comparatively noise power. A trivial way to prove (9) is to calculate the variance (Parseval theorem) before sampling, and to state that it is equal to the variance of the sampled signal. Accordingly, the phase noise is

(white, aliased -type) (10)

Oppositely, aliasing has negligible effect on flicker and on higher terms (, etc.). It follows from (8) that

(flicker, pure -type) (12)
Figure 2: Spectra originated by the phase type (-type) phase noise.

Figure 2 shows the spectral properties of the -type noise. Aliasing scales the white noise as , but it has no effect on flicker. The corner frequency which separates white from flicker regions is obtained equating (10) to (12)


3.2 Spectrum of the Time Type (-type) Phase Noise

The -type noise originates after the input comparator, where the clock signal has full SR and bandwidth. Though threshold fluctuations are always present, the voltage-to-time conversion has little effect, and the gate is characterized by its delay fluctuations. So, each gate of the clock distribution contributes to the delay, and the fluctuations add up statistically. At a closer sight, the device may be organized hierarchically, for example in gates and cells, likely with a longer propagation time between cells. Nonetheless, the fluctuation is proportional to the length and to the complexity of the distribution chain.

The pure -type noise is found in the region and below, not affected by aliasing. The noise spectrum is described by

(flicker, pure x-type) (15)

where is the technical parameter which results from the clock distribution.

The aliased -type results from sampling the fluctuation at the frequency , which affects the white noise region. The spectral parameter is found in the same way as with (9), neglecting the and higher terms

(white, aliased x-type) (17)
Figure 3: Spectra originated by the time type (-type) phase noise.

The spectral properties of the -type noise — i.e., (15)–(18) — are summarized in Fig. 3. The corner frequency which divides the flicker from the white region is calculated by equating (15) to (17)


3.3 Interpretation of Phase Noise Spectra

Figure 4: Comparison between -type and -type noise.

A series of spectra taken with several values of helps to understand the interplay of noise types. Scaling in powers of two seems appropriate.

Let us start with flicker, . Comparing (12) to (16), we expect that the noise is of the -type at low , and of the -type at high , with a corner frequency


This is shown in Fig. 4 A. Far from , we can evaluate

() (21)

The white phase noise is described by (10) at low , and by (18) at high , separated by the cutoff


This is shown on Fig. 4 B. At low , (10) enables to calculate the noise power of the input threshold


Assuming that is equal to 3–4 times the maximum , we can infer and the noise voltage . Conversely, at high we can extract the fluctuation


This can be compared to the rms jitter, if available in the specs.

4 Selected Noise Measurements

Figure 5: The digital phase meter is either a Symmetricom (now Microsemi) 5125 or 5120. The two outputs may have different frequency.

We measured the phase noise of several devices routinely used in our labs. This is a necessary step, before considering an unbound search for the best. Accordingly, the measurement method (Fig. 5) is more about flexibility than about sensitivity. Anyway, the phase noise of digital components is generally higher than that of common low noise components (i.e., amplifiers and mixers). On the other hand, we need simple operation in a wide range of frequency, with signals that may not be at the same frequency as the reference. For us, this is the relevant feature of the Microsemi 5125 (1–400 MHz) and 5120 (1–30 MHz) instruments. These instruments make use of correlation and average on the spectra of two nominally equal channels which measure the same quantity, which rejects the single channel noise [22, 23]. Notice that the oscillator is common mode, with very small differential delay, hence its noise is highly rejected. The Fourier frequency spans from 1 mHz to 1 MHz.

4.1 Cyclone III (65 nm)

Figure 6: Phase noise of the Cyclone III clock distribution.

In a first experiment, we measure a Cyclone III [24] in a clock buffer configuration. The input sinusoidal clock ( dBm on 50 ) is squared and distributed as in Fig. 1 A. The spectrum is shown in Fig. 6.

We first look at the white noise region. Our model suggests aliased -type noise (10) at low , and aliased -type noise (18) beyond the cutoff given by (23), as shown on Fig. 4 B. Starting from MHz, scales down as dB per factor-of-two, in fairly good agreement with the 3 dB predicted by the model. This results from the data fit shown on Fig. 6 top-right. Taking V, (10) gives a threshold fluctuation . The ‘ ’ results from ’ instead of the law. Assuming GHz (analog bandwidth, four times the maximum toggling frequency), we get . This is in agreement with general experience, which suggests that general high-speed electronics has a typical noise level of 10–15 .

At MHz, the white noise falls outside the 1 MHz span. Since this occultation occurs before the aliased -type noise shows up, we have no direct access to . On Fig. 6, at the maximum (1 MHz) and at 400 MHz carrier, the white noise is below (upper bound). This value, integrated over MHz and converted into time, gives 1 ps, which is an upper bound for .

Flicker noise is in good agreement with pattern of Fig. 4 B only at MHz. From this part of the plot, we calculate fs. By contrast, at MHz scales as dB per factor-of-two instead of being constant. This discrepancy is not understood. However, the region is rather irregular, and corrupted by bumps, even more pronounced at low .

The lowest flicker found on Fig. 6 ( at 3.125 MHz carrier), converted into voltage using (12), gives (upper bound for the input voltage flicker). Interestingly, this value is similar to the flicker of some CMOS high-speed operational amplifiers (for instance, 1.9 for the Texas Instruments OPA354A).

Figure 7: Phase noise of the Cyclone III, measured by comparing two outputs. Take away 3 dB for the noise of one buffer.

Figure 7 shows the phase noise of the output buffer. The white noise is too low to be visible with the 1 MHz span, masked by flicker and by some bumps at Hz. By contrast, the flicker noise is in perfect agreement with the 6 dB per factor-of-two model (pure -type noise). Comparing Fig. 7 to Fig 6, at MHz the flicker of the complete clock distribution is close to that of the output buffer. So, the contribution of the output buffer is not negligible. Conversely, at lower a significantly larger flicker rises in the clock distribution chain.

4.2 Measuring the Time Type (-Type) Noise with the Divider

After some tests, we realized that the frequency divider [25] is a good tool to measure the -type noise of the clock distribution. First, a frequency divider is useful in that the input time fluctuation (-type noise, (13)) is kept low by using a high input frequency, while the measurement at the lower output frequency is simpler (both instruments are suitable, and the background is lower). Second, the divider circumvents the aliasing phenomenon. In fact, a divider provides a triangle-like output waveform by combining phases of a square wave, which is equivalent to sampling at the input frequency.

Figure 8: Phase noise of some components used as a frequency divider in the configuration.

Figure 8 shows the phase noise of some devices used as dividers in configuration, with 100 MHz input and 10 MHz output frequency. The flicker coefficient is clearly identified, not corrupted by artifacts. The bump at 20 kHz (Zynq and Cyclone III) is due to the insufficiently filtered power supply. Finally, the divider implemented with the Max 3000 deserves mentioning for its low noise ( and ). This is lower than regular dividers (general experience), and just 10 dB above the NIST regenerative dividers [26] at the same output frequency.

5 The Volume Law

The idea that the phase noise coefficient is proportional to , where is the active volume, has been around for a while. In quartz resonators, this appears either directly or as a side effect of the larger size at lower frequency [27, 28, 29, 30, 31, 32]. In ultrastable Fabry-Perot cavities, flicker is powered by thermal noise and proportional to the reciprocal of the length [33, 34] which is approximately equivalent to after mechanical design rules.

The law results from a gedankenexperiment in which we combine equal and independent devices, giving . This has been confirmed experimentally with amplifiers [35, Chapter 2], [21]. Flicker is of microscopic origin because the probability density function is Gaussian, which originates from a large statistically-independent population through the central limit theorem. So, the devices can be combined in a factor-of- larger device exhibiting a factor-of- lower flicker. Similarly, we expect higher flicker if the size of the device is scaled down, until space correlation appears. The limit for small volume is not known.

In digital electronics, the volume of the active region is proportional to the node size . For reference, is of 10 m in Intel 4004 (1971), and of 16 nm in the Apple A10 Fusion chip of the iPhone 7. While the footprint surface is proportional to , the two scaling rules are common in the literature on VLSI systems, known as constant-voltage and Dennard [16, P. 253], [36], agree in the depth proportional to . Thus, . The wire delay may contain , however, the flicker associated to wires is too small to deserve attention [37].

Figure 9: Flicker coefficient of digital devices, related to the cell size .

We measured a few components using the divider configuration. This gives access to the noise of the clock distribution, which is of the -type. We used MHz, or MHz with the Cyclone and the Cyclone II for practical reasons, sharing a 5125A and a 5120A. The results are shown in Fig. 9, which compares the PM noise to .

The MAX V is not accounted for in the analysis because the spectrum was taken in unfavorable conditions, yet kept for completeness. A linear regression gives , with in nm. Fitting the same data with the exact volume law gives . The dB/dec slope is reasonably close to the law ( dB/dec), with a number of measurement and accuracy insufficient to assess a discrepancy.

6 Input Chatter

Figure 10: Simulation of carrier crossing a fluctuating threshold (normalized 1 Hz carrier, 1 ). Multiple crossing occurs in the center of the plot.
Figure 11: Example of chatter (multiple bouncing) when the input SR is insufficient as compared to the SR associated to noise.

Chatter is a fast random switching of a comparator, which occurs in the presence of wideband noise when the mean square slew rate of noise exceeds that of the signal at the threshold, i.e., . The phenomenon is shown in Fig. 10 and 11.

Following the Rice’s approach [38, 39], noise in the small interval can be represented as the sinusoidal signal , which has random amplitude , random phase , and slew rate


The Parseval theorem requires that , thus


because in . The mean square slew rate is calculated combining (26) and (27), integrating on frequency, and averaging on . Since ,


In turn, is determined by white noise , . Other noise types are negligible because they occur al low frequency, compared to , and because of the term in (28). Thus


Since the clock signal (7) has slew rate , the chatter threshold is


Taking the Cyclone III parameters (Sec. 4.1, GHz and , thus  ), and MHz, (30) suggests a threshold  mV. On Fig. 11, we see that chattering occurs at  mV, and at  mV the transitions are broken. Given the difficulty of identifying the parameters, the agreement between model and observation is satisfactory.

After (30), chattering is more likely at low carrier frequency. However, Fig. 11 shows that this can occur at 5 MHz, a standard frequency of great interest for high stability signals.

7 Internal PLL

Figure 12: Cyclone III internal PLL frequency multiplier.

The internal PLL is intended to provide high frequency internal clock stabilized to an external reference, often 5-10-100 MHz. We show simple experiments which give insight in the Cyclone III.

The PLLs is shown in Fig. 12. The VCO operates in the 0.6–1.3 GHz range, extended to 300–650 MHz by the optional divider, always present in our tests. A classical phase-frequency detector (PFD) is present, with charge pump output driving the analog feedback to the VCO. The PLL output frequency is . This leaves three degrees of freedom (, and ), two of which are available to the designer. The programming tool (Quartus) uses one to ensure that internal design rules are satisfied.

The VCO relies on a LC resonator on chip. General literature suggests a quality factor of 5–10, limited by the technology [40]. Therefore, we expect a Leeson frequency of the order of 50 MHz.

Figure 13: The internal PLL is used as a buffer, that is, .

In a first experiment (Fig. 13), we use the PLL as a ‘cleanup’ (), yet with a high purity input. This gives the noise of the PLL, at different values of . For lowest noise, we use the phase comparator at the highest possible frequency () by setting . The VCO frequency ends up to be 400, 600 or 640 MHz, depending on . On Fig. 13, the white noise floor is not seen. This is sound because noise can be white only beyond , which is beyond the 1 MHz span. Flicker is of the -type at 5 and 10 MHz, with ( dB). Since this type of noise is not scaled down by the divider in the loop, we ascribe it to the phase detector. This is because (i) with the tight lock implemented we do not expect to see the VCO; and (ii) the input comparator and the output stage of the divider have some 10 dB lower noise in similar conditions ( , Section 4.1).

Figure 14: The internal PLL is used as a frequency multiplier in powers-of-two of multiples of the 10 MHz frequency reference.

In the second experiment, we use the PLL as a frequency multiplier in powers of two () from 10 MHz to 640 MHz, with MHz. Again, we use for lowest noise. The VCO delivers 320, 400 or 640 MHz, depending on . The phase noise spectrum (Fig. 14) indicates that flicker is of the -type, scaling up as . This indicates that the phase detector is the dominant source of noise, with negligible contribution of the dividers. So, the time fluctuation is transferred from the phase detector to the VCO, and then from the VCO to the output. The phase scales accordingly, that is, .

8 Thermal Effects

8.1 Thermal Transients

Common sense suggests that delay is affected by the junction temperature , while other parameters like and (case and ambient temperature) are comparatively smaller importance.

Our method consists in using the electrical power to heat the chip, and calculate from the thermal resistance and the transients. In turn, is chiefly set by the charge/discharge cycle of the gate capacitance, whose energy is . Thus, gates switching at dissipate . Of course, can be changed instantaneously. The delay is measured with a Symmetricom 5125A test set used as a phase meter and also as a time-interval counter.

We measured a Cyclone III used as a clock buffer (actually, 10 buffers connected in parallel through 330  resistors). The temperature had to be low-pass filtered by covering the card with a small piece of tissue. The results are shown in Fig. 15.

Figure 15: Thermal effects measured on a Cyclone III FPGA. Each curve represents the thermal transient when the clock frequency is divided by two.

In the main body, all the curves show an exponential behavior plus a linear drift


where results from setting in powers of two, and is the time constant. For reference, we observed W at 400 MHz, which means K with K/W (including the thermal pad on the pcb), and neglecting the dissipation at .

The linear drift (1 fs/s, or fractional frequency) does not scale with power. This behavior is typical of the environment temperature, slowly drifting during the measurement (a fraction of a Kelvin over 1 hour). Extrapolating the drift to , we get the asymptotic effect of the transient alone.

The time constant is found as the intercept of the tangent at and the linear drift (dashed lines). This graphical process removes the drift. The value s is the same for all the transients.

The inset of Fig. 15 shows the delay versus the carrier frequency (dissipated power). As expected, the delay is proportional to , set through . Accounting for and , the thermal coefficient of the delay is ps/K.

8.2 Allan Deviation

Figure 16: Allan deviation derived from the FPGA delay.

Generally, should follow the law (white and phase noise). Other types of instability, as frequency noise would reveal a phase noise steeper than , and the delay of the device would diverge in the long run. However, bumps may be present. Notice that phase noise in practice never yields large integrated delay.

Figure 16 shows the Cyclone III Allan deviation , measured with a Symmetricom 5125A test set.

We first discuss the region of Fig. 16 A. At low , decreases proportionally to . For s, we read at 3.125 MHz, at 6.25 MHz, etc. At higher the curves get closer to one another, and overlap at MHz.

Taking the classical conversion formulae for Allan variance and spectra (for example, [41, P. 77–80], or [17]), the behavior is equivalent to (frequency fluctuation spectrum ), thus to vs. . This is the signature of the pure -type noise, as expected at low and at low , thus at long . We recall that the fluctuation of the input threshold is dominant at low , and that the low region is dominated by the phase noise, virtually unaffected by aliasing.

By contrast, the vs.  behavior is equivalent to vs. , thus . This is the typical of the pure -type noise, as expected at high and at low , thus at long . The fluctuation of the input threshold is no longer relevant, and the low region is still dominated by the phase noise, virtually unaffected by aliasing.

In summary, the region of the plot is consistent with the predictions of Section 2.

On the right hand of Fig. 16 A, seems to leave the law. This can only be a local phenomenon, i.e. a bump. Carrying on the experiment, in Fig. 16 A the measurement of restarts immediately after switching , while in Fig. 16 B the measurement of is delayed by 1 hour after switching . The relevant difference is that in A each curve suffers from the cooling-down transient of the previous measurement, while in B each measurement starts in steady state. Bumps show up in A at s, and they get stronger at higher , where the thermal dissipation is stronger, and almost disappear in B. This is a qualitative confirmation of the presence of two separate time constants (end of Sec. 8.1).

8.3 Side Effects of the Thermal Dissipation

We have shown that the electrical activity inside the FPGA heats the chip, and in turn affects the delay. Variations exceeding 50 ps have been observed in the presence of a light burden. The analysis gives a warning, thermal crosstalk is around the corner when the same FPGA is in charge of more than one task, made worse by the heat latency. Attempts to fit low noise and high-stability functions (frequency dividers, etc.) in a chip processing at high rate may be difficult or give unpredictable results.


This work is a part of the “Programme d’Investissement d’Avenir” projects in progress in Besancon, i.e., Oscillator IMP, First-TF, and Refimeve+. Funds come from the ANR, the Region Franche Comté, INRIM, and EMRP Project IND 55 Mclocks.

We thank the Go Digital Working Group for general help and fruitful discussion, and among them chiefly Jean-Michel Friedt, Pierre-Yves “PYB” Bourgeois, and Gwenhael “Gwen” Goavec-Mérou.


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