On Constructing Secure and Hardware-Efficient Invertible Mappings
Our society becomes increasingly dependent on wireless communications. The tremendous growth in the number and type of wirelessly connected devices in a combination with the dropping cost for performing cyberattacks create new challenges for assuring security of services and applications provided by the next generation of wireless communication networks. The situation is complicated even further by the fact that many end-point Internet of Things (IoT) devices have very limited resources for implementing security functionality. This paper addresses one of the aspects of this important, many-faceted problem - the design of hardware-efficient cryptographic primitives suitable for the protection of resource-constrained IoT devices. We focus on cryptographic primitives based on the invertible mappings of type . In order to check if a given mapping is invertible or not, we generally need an exponential in number of steps. In this paper, we derive a sufficient condition for invertibility which can be checked in time, where is the size of representation of the largest function in the mapping. Our results can be used for constructing cryptographically secure invertible mappings which can be efficiently implemented in hardware.
Invertible mapping, permutation, Boolean function, NLFSR
This paper addresses the problem of constructing hardware-efficient cryptographic primitives suitable for assuring trustworthiness of resource-constrained devices used in services and applications provided by the next generation of wireless communication networks.
The importance of improving security of wireless networks for our society is hard to overestimate. In 2014, the annual loss to the global economy from cybercrimes was more than $400 billion . This number can quickly grow larger with the rapid growth of Internet-of-Things (IoT) applications. In coming years ”things” such as household appliances, meters, sensors, vehicles, etc. are expected to be accessible and controlled via local networks or the Internet, opening an entirely new range of services appealing to users. The ideas of self-driving cars, health-tracking wearables, and remote surgeries do not sound like science-fiction any longer. The number of wirelessly connected devices is expected to grow to a few tens of billions in the next five years .
Unfortunately, the new technologies are appealing to the attackers as well. As processing power and connectivity become cheaper, the cost of performing a cyberattack drops, making it easier for adversaries of all types to penetrate networks. Attacks are becoming more frequent, more sophisticated, and more widespread. A connected household appliance becomes a target for all hackers around the globe unless appropriate security mechanisms are implemented. Household appliances typically do not have the same level of protection as computer systems. A compromised device can potentially be used as an entry point for a cyberattack on other devices connected to the network. The first proven cyberattack involving ”smart” household appliances has been already reported in . In this attack, more than 750.000 malicious emails targeting enterprises and individuals worldwide were sent from more than 100.000 consumer devices such as home-networking routers, multi-media centers, TVs, refrigerators, etc. No more than 10 emails were initiated from any single IP-address, making the attack difficult to block based on location. The attack surface of future IoT with billions of connected devices will be enormous.
In addition to a larger attack surface, the return value for performing a cyberattack grows. The assets accessible via tomorrow’s networks (hardware, software, information, and revenue streams) are expected to be much greater than the ones available today, increasing incentive for cyber criminals and underground economies . A growing black market for breached data serves as a further encouragement. The damage caused by an individual actor may not be limited to a business or reputation, but could have a severe impact on public safety, national economy, and/or national security.
The tremendous growth in the number and type of wirelessly connected devices, as well as the increased incentive for performing attacks change the threat landscape and create new challenges for security. The situation is complicated even further by the fact that many end-point IoT devices require utmost efficiency in the use of communication, computing, storage and energy resources. A typical IoT device spends most of its ”life” in a sleep mode. It gets activated at periodic intervals, transmits a small amount of data and then shuts down again. To satisfy extreme limitations of resource-constrained IoT devices, very efficient cryptographic primitives for implementing encryption, data integrity protection, authentication, etc. are required.
Invertible mappings are among the most frequently used primitives in cryptography . For example, the round function of a block cipher [6, 7] has to be invertible in order to result in unique decryption. Stream ciphers [8, 9] and hash functions [10, 11] use invertible state mappings to prevent incremental reduction of the entropy of the state.
This paper presents a sufficient condition for invertibility of mappings of type . Such a single-variable -valued mapping can be interpreted as an -variable Boolean mapping in which the Boolean variable represents the bit number of the input and the Boolean function represents the bit number of the output , i.e.:
for . For example, the 4-variable Boolean mapping
corresponds to the single-variable 16-valued mapping
where “” is addition modulo 16. Note that the corresponding single-variable -valued mapping may not have a closed form.
In order to check if a mapping of type (1) is invertible or not, we generally need an exponential in number of steps. The condition derived in this paper can be checked in time, where is the size of representation of the largest Boolean function in the mapping. So, it can be used for constructing secure invertible mappings with a small hardware implementation cost. For example, we show how the presented results can be used in stream cipher design.
The paper is organized as follows. Section II summarizes basic notations used in the sequel. In Section III, we describe previous work and show that previous methods cannot explain invertibility of some mappings which can be handled by the presented approach. Section IV presents the main result. Section V estimates the complexity of checking the presented condition. Section VI shows how the presented results can be used in stream cipher design. Section VII concludes the paper.
Throughout the paper, we use ”” to denote the Boolean XOR, ”” to denote the Boolean AND and to denote the Boolean complement of , defined by .
where are constants, “” is the Boolean AND, “” is the Boolean XOR, the vector is the binary expansion of , and denotes the th power of defined by for and otherwise, for .
The dependence set (or support set ) of a Boolean function is defined by
where for .
A mapping on a finite set is called invertible if if, and only if, . Invertible mappings are also called permutations.
Iii Previous Work
In this section, we describe previous work on invertible mappings and show that previous methods cannot explain invertibility of some mappings which can be handled by the presented approach.
Many methods for constructing different classes of invertible mappings are known. The simplest one is to compose simple invertible operations. A Substitution-Permutation Network (SPN) is a typical example. An SPN consists of S-boxes, which permute input bits locally, and P-boxes, which diffuse input bits globally. This method of construction cannot explain the invertibility of, for example, the following 4-variable mapping
since a non-invertible operation Boolean AND is used.
Feistel  proposed a powerful technique which makes possible constructing invertible mappings from non-invertible basic operations. It is used in many block ciphers, including DES . The basic Feistel construction maps two inputs, and , into two outputs as follows:
where is any single-variable function. The full Feistel construction iterates the above mapping any number of times. This method was extended in several directions, including unbalanced, homogeneous, heterogeneous, incomplete, and inconsistent Feistel networks . However, the Feistel construction requires at least two variables. It cannot explain the invertibility of mappings of type . The presented method can explain it by looking into the structure of Boolean functions representing the bits of the output .
where and are arbitrary non-zero -variable polynomials modulo a large RSA modulus . The ”triangular” nature of functions makes it possible to perform the inversion process similarly to the way we do Gaussian elimination to solve a system of linear equations. This approach can also handle ’s and ’s which mix arithmetic and Boolean operations [19, 20]. The approach presented in this paper is similar to the approach of Shamir in that it also uses triangulation to prove invertibility. However, our functions are of the type
where and does not depend on . Thus, in our case, the th output may depend on the input such that . For example, in the mapping defined by equations (2), depends on and .
Shamir’s construction was further extended by Klimov and Shamir [19, 20] to a class on invertible mappings based on T-functions. A single-variable function of type is defined to be a T-function if each of its output bits depends only on the first input bits :
A T-function is invertible if, and only if, each output bit can be represented as
This fundamental result inspired the construction which we present in this paper. The reader will easily notice that, in our construction (3), functions ’s are T-functions while functions ’s are not if . Another difference is that Klimov and Shamir targeted software implementation and therefore focused on mappings whose expression can be evaluated by a program with the minimal number of instructions. We target the hardware implementation. Therefore, we are interested in minimizing the number of Boolean operations in the expressions of Boolean functions representing output bits. The construction method which we present can be used as a starting point for constructing nonlinear invertible mappings which have an efficient hardware implementation.
Another group of construction methods consider permutation polynomials which involve only the arithmetic operation of addition, subtraction, and multiplication. Permutation polynomials are well-studied in mathematics. Hermite  made a substantial progress in characterizing univariate permutation polynomials modulo a prime . Dickson  described all univariate polynomials with degrees smaller than 5. However, the problem remains unsolved for high degree polynomials modulo a large prime .
The problem appears simpler for the ring of integers modulo . Rivest  provided a complete characterization of all univariate permutation polynomials modulo . He proved that a polynomial
with integral coefficients is a permutation polynomial for if, and only if, is odd, is even and is even. His powerful algebraic proof technique was further generalized by Klimov and Shamir [19, 20] to polynomials of type
where , which mix arithmetic and Boolean operations. However, since the resulting polynomials are T-functions, they do not cover the construction method presented in this paper for the case when th output depends on the input such that .
Finally, we would like to discuss the relation between the mappings of type (1) and the state mappings generated by Non-Linear Feedback Shift Registers (NLFSRs) . An -bit NLFSR consists of binary stages, each capable of storing 1 bit of information, a nonlinear Boolean function, called feedback function, and a clock (see Figure 1). At each clock cycle, the stage is updated to the value computed by the feedback function. The rest of the stages shift the content of the previous stage. Thus, an -bit NLFSR with the feedback functions implements the state mapping of type
where the variable represents the value of the stage , for .
It is well-known  that an -bit NLFSR is invertible if, and only if, its feedback function is of type
The mappings considered in this paper can be implemented by a more general type of non-linear state machines, shown in Figure 2. Since the content of stages is not any longer shifted from one stage to the next, but rather it is updated by some arbitrary functions, such registers are not called shift registers any longer. Instead, they are called binary machines  or registers with non-linear update . Binary machines are typically smaller and faster than NLFSRs generating the same sequence [27, 28]. For example, the 4-bit NLFSR with the feedback function generates the same set of sequences as the 4-bit binary machine implementing the 4-variable mapping defined by equations (2). We can see that the binary machine uses 3 binary Boolean operations, while the NLFSR uses 5 binary Boolean operations. Furthermore, the depth of feedback functions of the binary machine is smaller that the depth of the feedback function of the NLFSR. Thus, the binary machine has a smaller propagation delay than the NLFSR.
Iv Conditions for Invertibility
The proof is simple, because every two consecutive states of an NLFSR overlap in positions. This implies that each state can have only two possible predecessors and two possible successors. If is in the form (4), then the NLFSR states which correspond to the binary -tuples and always have different successors. The values of and depend on the value of and on the value of . The value of is the same for and . The value of is different for and . Thus, . It is also easy to see that, if both and have the same successor, cannot have the form (4).
In the general case of mappings , any binary -tuple can have possible predecessors and possible successors. Therefore, to guarantee that a mapping is invertible, we have to check that, for all , implies that , for some . This clearly requires the number of steps which is exponential in . The main contribution of this paper is a more restricted sufficient condition which can be checked in steps. To formulate this condition, we first introduce the notion of a free variable of a function.
Definition 1 (Free variable)
A variable is called a free variable if can decomposed as
Definition 2 (Set of free variables)
The set of free variables of , , contains all free variables of
Now we are ready to formulate the following sufficient condition for invertibility.
A mapping of type (1) is invertible if the following two conditions hold:
For each , is of type
Functions can be re-ordered as to satisfy the property
where “” stands for the union.
Proof: By contradiction.
Suppose that there exist a non-invertible mapping of type (1) for which the conditions of the theorem hold. Then, this mapping is of type
where , for .
and and implies
and and and implies
and and and , , implies .
Therefore, . We reached a contradiction. Thus, the assumption that there exist a non-invertible mapping of type (1) for which the conditions of the theorem hold is not true.
An example of mapping which satisfies the conditions of Theorem 1 is:
The reader may notice that mappings defined by Theorem 1 can be obtained by re-labeling variables in a T-function. The re-labeling is given by the ordering of free variables. So, the mapping (5) can be viewed as a composition of a bit permutation and a T-function. Since there are bit permutations, the class of invertible mappings considered in this paper is by a factor of larger than the class of invertible mappings based on T-functions.
Clearly, the re-labeling of variables does not change the implementation cost of a mapping. However, it might drastically change the cycle structure of the underlying state transition graph, as illustrated by the following example. Consider the following 4-variable mapping based on a T-function:
This mapping has a quite uninteresting state transition graph shown in Figure 3. Let us re-label the variables as . We get the mapping:
which has the state transition graph shown in Figure 4. All states, except the all-0 state, are included in one cycle. If we implement this mapping by the binary machine shown in Figure 2 and initialize the binary machine to any non-zero state, then its output generates a pseudo-random sequence with period 15 which satisfies the first two randomness postulates of Golomb , namely the balance property and the run property. No sequence generated by a nonlinear Boolean function satisfy the third randomness postulate (two-level autocorrelation property). Therefore, the mapping we obtained by re-labeling has much more interesting statistical properties than the original mapping.
The cycle structure of a mapping is important for some cryptographic applications, e.g. stream ciphers . Obviously, if we iterate a mapping a large number of times, we do not want the sequence of generated states to be trapped in a short cycle. It is worth noting that formal verification tools based on reachability analysis can be adopted for finding short cycles in a state transition graph. There are dedicated tools to compute the number and length of cycles in state transition graphs of synchronous sequential networks, e.g. BNS  which is based on SAT-based bounded model checking and BooleNet  which is based on Binary Decision Diagrams.
The mappings defined by Theorem 1 are invertible for any choice of Boolean functions . The smaller is the number of Boolean operations in the expressions of ’s, the smaller is its hardware implementation cost. Note, that we are not restricted to represent ’s in ANF. Any Boolean expression combining AND, OR, NOT and XOR can be used. Multi-level logic optimization tools, such as UC Berkeley tool ABC  can be applied to transform the ANF or other Boolean expression representing the function into an optimized multi-level expression. Clearly, the choice of ’s will be guided not only by the hardware cost, but also by other criteria determining the cryptographic strength of the resulting function, e.g. nonlinearity, correlation immunity, algebraic degree, etc. (see  for requirements on cryptographically strong functions).
Finally, we would like to point out that the conditions of Theorem 1 are sufficient, but not necessary conditions for invertibility. For example, the following 4-variable mapping is invertible, but it does not satisfy them:
V Condition Checking
Next, let us estimate the number of steps required to check the conditions of Theorem 1. Suppose that all Boolean functions of the mapping are represented in ANF. Let be the ANF size of the largest function in the mapping. The size of an ANF is defined as the total number of variables appearing in the ANF. For example, the ANF is of size 3.
Consider the pseudocode shown as Algorithm 1. is a set which keeps track of variables which are identified as free for some . If this set is implemented as a hash table of size , then adding a variable to the set or checking if a variable belongs to the set can be done in constant time.
In the first for-loop, we check if each is of type or , for some . If yes, we add to the set and mark . Since the steps 4, 5, 6 and 7 can be done in time, the complexity of the first for-loop is .
If none of the functions are marked during the first for-loop, the algorithm terminates with the conclusion that the conditions of Theorem 1 are not satisfied.
In the second for-loop, for each non-marked , we check if it is of type (5) and if every belongs to . If yes, add to , mark , and return to step 13. The steps 15, 17 and 18 can be done in time. The step 16 requires time. Thus, the complexity of the second for-loop is . Since we return to the step 13 at most times, the overall complexity of steps 13-22 is .
In the third for-loop, we check if all are marked. If yes, the mapping is invertible. Otherwise, the algorithm returns ”conditions are not satisfied”. Since the conditions of Theorem 1 are sufficient, but not necessary conditions for invertibility, in this case the mapping may or may not be invertible. The complexity of the third for-loop is . We can conclude that overall complexity of Algorithm 1 is .
In this section we show how the presented results can be used in stream cipher design.
A possible way to construct a key stream generator for a stream cipher is to run several FSRs in parallel and to combine their outputs with a nonlinear Boolean function . The resulting structure is called a combination generator. If the periods of FSRs are pairwise co-prime, then the period of the resulting key stream generator is equal to the product of periods of FRSs . Examples of stream ciphers based on combination generators are VEST , Achterbahn-128/80 , and the cipher . VEST uses 16 10-bit and 16 11-bit NLFSRs. Achterbahn-128/80 uses 13 NLFSRs of size from 21 to 33 bits. The cipher from  uses 10 NLFSRs of size 22-29, 31 and 32 bits.
At present it is not known how to construct large NLFSRs with a guaranteed long period. Existing algorithms cover special cases only, e.g. [37, 38]. Small NLFSRs which are used in combination generators are computed by a random search. Lists of -bit NLFSRs of size bits with the period whose feedback functions contain up to 6 binary Boolean operations in their ANFs are available in . It is known that, for example, there are no 20-bit NLFSRs with the period whose feedback function contains only four binary Boolean operations in its ANF (i.e. implementable with four 2-input gates).
Using Algorithm 1 to bound random search, in 12 hours we were able to find 63 20-variable nonlinear invertible mappings with the period whose functions contain no more than 4 binary Boolean operations in their ANFs in total. Two representatives are:
, , .
The omitted functions are of type , for . This shows that Algorithm 1 is useful for finding nonlinear invertible mappings with a small hardware implementation cost. Other important properties, such as nonlinearity, correlation immunity, algebraic degree, etc., can then be used to further guide the search.
We derived a sufficient condition for invertibility of mappings of type which can be checked in steps, where is the ANF size of the largest Boolean function in the mapping. The presented method can be used as a starting point for constructing nonlinear invertible mappings which can be efficiently implemented in hardware.
Future work remains on constructing new cryptographic primitives based on the presented class of invertible mappings and evaluating their security and hardware cost. We also plan to investigate the usability our results in reversible computing.
This work was supported in part by the research grant No SM14-0016 from the Swedish Foundation for Strategic Research. The author would like to thank the anonymous reviewers for their valuable comments and suggestions to improve the quality of the paper.
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