Memcapacitive Devices in Logic and Crossbar Applications

Memcapacitive Devices in Logic and Crossbar Applications

Dat Tran Department of Electrical and Computer Engineering
Portland State University, Portland, OR, USA
   S. J. Department of Electrical and Computer Engineering
Portland State University, Portland, OR, USA
   Christof Teuscher Department of Electrical and Computer Engineering
Portland State University, Portland, OR, USA

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about for the MNIST dataset and a factor of about for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications.

memcapacitor, memristor, logic, crossbar, classifier

CT \addeditorDT

1 Introduction

The ever-growing demand for more speed and lower power in circuit design poses significant challenges for the continuing scaling of today’s CMOS technology. Fundamental physical as well as architectural limits lead to new bottlenecks. While the advent of multicore architectures alleviated some of the challenges, more cores do not always mean better: only a fraction of the cores typically operate at full speed because of Amdal’s law and power constraints [12]. Finding alternative devices and architectures beyond CMOS, beyond Boolean logic, and beyond von Neumann architectures has been a major driver of the unconventional computing community.

Memristive devices [44] have been widely adopted in previous years for various conventional and unconventional applications. They have shown great promise for high integration densities as well as low energy consumption [38, 41, 17], for example for neuromorphic applications [23, 15, 22, 58, 46] and for memristor-based logic circuit design [49]. However, the energy consumption of memristors is bounded by the resistive nature of these devices. That is where memcapacitors [29, 4], another mem-element, may have further benefits.

Recent work demonstrated a memcapacitive response in a mono-layer metal insulator devices [20], in a metal-insulator composite of , , and [56], in organic polymer layers embedded with graphene sheets [32], in a nano device of polyvinyl alcohol/cadmium sulphide [40], and in a hafnium oxide () on n-type Si substrate [54]. Mohamed et al. discovered that it is possible to construct a memcapacitive device from a memristive metal-oxide composite by adjusting the physical device parameters [29]. The memcapacitive characteristics of the device solely depend on a behavior shape factor (BSF), which is controllable during the fabrication process. Mohamed et al. derived a mathematical model that describes the response of a metal-oxide device based on the device state, the capacitive current, and the tunneling current. When the behavior shape factor is less than , the capacitive current becomes dominant and the device operates as a memcapacitor [29]. Biolek et al. designed a SPICE model that describes the correlation between electrical charge and voltage using a dependent voltage-controlled current source [4]. Their SPICE model produced the predicted results of a bipolar memcapacitive model with threshold through simulations in PSpice, LTspice, and HSPICE.

Several applications of memcapacitive devices have been proposed, such as the dynamic configurations of transmission lines [34], improving a cellular neural network’s density [55], a memcapacitive synapse with integrate-and-fire neurons [33], dynamic computing random access memory [47], and biomimetic sensors [7]. Logic applications, combined with CMOS inverters, have been demonstrated for both memristors [26, 1] and memcapacitors [47]. Similar to memristive logic gates, which can improve the chip density by a factor of compared to CMOS gates [8], memcapacitive logic gates are equally promising for an increased area density. While memristive crossbars are widely adopted for machine learning applications, such as pattern classification [2, 57], high-speed image processing [16], and random access memory [50], memcapacitive crossbars, to the best of our knowledge, were only introduced in [45, 13] but not fully explored in this context.

In this paper, we propose two novel memcapacitor applications: (1) binary switching in digital logic and (2) analog computing in a crossbar classifier. Our main contributions include a new set of memcapacitive logic gates as well as a memcapacitor-based crossbar classifier. Our results show that both memcapacitor architectures are significantly more energy-efficient while performing similarly compared to memristor-based architectures. The work expands the foundations of computing with memcapacitive devices and is relevant for applications where low power is critical, such as mobile platforms, the Internet of Things (IoT), and embedded systems.

2 Background

Although memcapacitive behaviors were observed in several composite devices [20, 56, 32, 40, 54], only two models are currently available in the literature: the Biolek model [4] and the Mohamed model [29]. These two models are selected for our studies.

The Biolek model describes a memcapacitive behavior of an ideal device with a threshold. The memcapacitance functions as an internal variable and is related to the electric charge and the applied voltage [4]:

where is a function that describes the threshold property and is a window function. These functions are defined as:

is a device constant expressing how the memcapacitance changes when , is a threshold voltage, is a step function, and and are the minimum and maximum values of the device’s capacitance.

Figure 1: Charge-voltage response of the Biolek model [4] and the Mohamed model [29].

The Mohamed model depicts the memcapacitive response of a metal-dioxide device. The correlations of the device states ( and ), the memcapacitance , and applied voltage are as following [29]:

where is the filament growth due to ion migrations between the metal-dioxide gap, is the cross section area of the filament, and is a window function defined in [3]. The memcapacitance is a function of the device’s total capacitance. This function depends on the permittivity of the gap insulator , the gap cross section , and the maximum gap thickness . The derivatives of the state variables and model the growth/shrinkage of the filament, which is controlled by the tunneling current and the capacitive current [29].

Fig. 1 shows the charge-voltage responses of the Biolek [4] model and the Mohamed model [29]. As one can see, the responses follow a pinched hysteresis loop, which is the fundamental characteristic of a mem-device. The threshold voltage of the Biolek model was set to 0.8V. The threshold voltage was added to the original Mohamed model and the constants were modified to deal with a low input frequency of 1Hz: , and .

3 Proposed Memcapacitive Circuits

3.1 Memcapacitive Logic Gates

Logic gates form the fundamental building blocks of digital circuits and architectures. It was proven that both memristors [25] and memcapacitive devices [35] are capable of performing logic operations using material implications. Several studies have shown that logic gates can be realized with memristors [8, 1] and that such gates consume less power and allow for higher integration densities than CMOS gates. The first design of memristive gates was developed for fuzzy logic [24], which was extended to include sorting networks [30]. It was show to be compatible with CMOS AND/OR functionality [26]. The main idea for designing a memristive logic gate is based on voltage division: several resistors connected in series can scale an applied voltage to different voltages according to their resistance values. Unlike traditional fixed-value resistors, memristors have the ability to alter their resistance to an ON state (low resistance) or OFF state (high resistance). The voltages across them can therefore change dynamically. If the ON/OFF resistance ratio is sufficiently large, each memristor in a memristive gate can operate as a binary switch, analogous to a CMOS switch. Here, we apply the same concept to memcapacitive gates since such devices, when connected in series, can also scale voltages according to their dynamic capacitance.

Figure 2: 2-input and 3-input memcapacitive AND gates.
Figure 3: 2-input and 3-input memcapacitive OR gates.

Considering the 2-input gate in Fig. 2, and are in series with respect to inputs a and b. The electric charge is the same for both devices:


Assuming that with 0V for logic 0 and 1V for logic 1, we consider four cases for the output according to Eq. 4:

  • :

  • : with their connection polarities, is switched to , is switched to , and the output voltage is:

    where is the upper limit voltage for logic 0.

  • : is switched to , is switched to , and the output voltage is:

  • : the output voltage is:

The input combinations of and along with the output values of constitute the truth table of an AND gate.

Similarly, for the 2-input OR gate (Fig. 3) and from on the Eq. 4, we consider four cases:

  • :

  • : is switched to , is switched to , and the output voltage is:

    where is the lower limit voltage for logic 1.

  • : with their connection polarities, is switched to , is switched to , and the output voltage is:

  • : the output voltage is:

Here, the input combinations of and and the corresponding output values represent the truth table of an OR gate. Similarly, 3-input or 4-input AND and OR memcapacitive gates can be built.

It is known [51] that any logic expression can be described as a combination of AND, OR, and NOT functions. The NOT function generally requires an active element to complement its input signal. Since memcapacitive devices are passive, the NOT function cannot be implemented. As a consequence, we still need to rely on a traditional CMOS inverter to obtain a complete set of memcapacitive gates.

3.2 Memcapacitive Crossbar Classifier

Crossbar architectures are attractive due to the regularity and the integration density. They have become more popular for memristive devices for these reasons [5, 19, 36, 37]. It has previously been shown that a general memcapacitive crossbar network can be built [45] and that such a crossbar network can perform a dot product [13].

Figure 4: Memcapacitive crossbar network. The role of the termination output capacitors is to convert the total electric charge in each column to a corresponding voltage .

For our purpose, we propose the memcapacitive crossbar network as shown in Fig. 4. This network functions as a classifier and can perform a dot product without the need of a processor and a memory as specified in [13]. In this network, the memcapacitive devices are located at the nano-wire junctions. Each column has a termination capacitor that converts the total charge in column to an equivalent voltage , which can then be measured. The crossbar also has a bias column. In our previous work on memristor crossbar architectures [52], we showed that a bias column is needed to compensate for currents in columns where all memristive devices are at . represented a weight value of zero (), whereas represented a value of one (). Without a bias column, will still produce a small current in reality. The crossbar, which essentially computes a dot product, then results in an actual zero value when the bias column is used to compensate for the non-zero currents. This is essential for the training and testing of the crossbar classifier.

We use the same approach for the memcapacitive crossbar classifier. From an electrical point of view, (the minimum capacitance of a memcapacitive device) at a column still allows a small charging current. Compensating for this current with the bias column ensures a zero dot product. In our memcapacitive crossbar network, all memcapacitive devices at the bias column were set to their minimum capacitance, which is equivalent to a zero weight.

Figure 5: Virtual ground module. The OpAmp provides a virtual ground. Charge from output column is compensated by charging or discharging currents through the capacitor .

An inherent issue of any crossbar network is the effect of sneak-path currents. Several solutions have been proposed for memristive crossbar networks to overcome this problem: multistage readings [48], unfolded networks [28], complimentary reading algorithm [18], virtual ground [53], or adapting three-terminal devices [59]. From Fig. 4, the undesired paths allow additional charge from other columns to go to output capacitors and , which then hold the total charge at only columns 1 and 2.

For our memcapacitive crossbar, we propose a capacitive virtual ground module as shown in Fig. 5 at each output column. The 0V ground reference, provided by the OpAmp at each column , eliminates all sneak-path currents. With the absence of sneak-path currents, voltage pulses at the input rows will charge the memcapacitive devices according to their internal capacitance states . The total charge at a particular column is then accumulated and transferred to the output capacitor in the virtual ground module. The total charge at column is given by:


where is the electric charge stored in a memcapacitive device at the connective junction and is the total electric charge of the bias column.

The subtractive term ensures that the total charge is zero when all memcapacitive devices at column are at their minimum capacitance. Expanding and simplifying Eq. 5, the output voltage at output column becomes:


where is the capacitance of a memcapacitive device at junction , bounded by the interval .

Eq. 6 shows that the output voltage at column is proportional to the device capacitance and , the input voltage , and the output capacitance . The output voltage is independent of charge , the total charge of all memcapacitive devices at column . As a result, our memcapacitive crossbar does not suffer the large effect of charge leakage as reported in [60] for a MOS-gated memristor array.

4 Results

4.1 Mem-devices in Logic Applications

We used a pulse width and an amplitude to represent logic 1. To verify the logic gates, pulses were generated from the signal sources to simulate all the input states of a -input gate. In addition, we measured the average power consumption of the memcapacitive gates and compared the values with equivalent memristive as well as CMOS gates.

According to [24], a valid output voltage of a memristive gate depends significantly on the changing states (switching from to or vice versa) of the device and a high ratio of and . This changing state is linked to two physical factors of a memristive device, which vary from device to device: threshold voltage and switching time . An applied pulse has to be sufficiently large () and long () so that the memristive devices can change their internal states and produce the correct outputs. Table 1 lists the switching times of all mem-devices we used here.


max width= Model Dev Pulse Switching Time of Ampl Width Type Biolek [4] 2.4 Mohamed[29] 2.4 Chang [6] 2.4 Oblea [31] 2.4 Sheridan [42] 4.85

Table 1: Switching times of mem-devices. stands for a memcapacitive and for a memristive device. is the internal state of a device. Each device was tested with a single pulse of amplitude and width . The switching time was determined by measuring the change of its internal state from 1% to 98% () or from 98% to 1% () of its initial value.

We selected three memristive models in Table 1 for their stability and their high ratio. The Oblea device had the lowest switching time of (at the exception of the Mohamed device). We therefore used logic pulses of for all simulated mem-device gates and pulses for the Mohamed memcapacitive gates. Note that the switching time of the Mohamed memcapacitive gate was so long because of the very slow convergence of the device’s internal state from 1% to 98% of once it passed the 90% point. The original Mohamed memcapacitive model was developed for an input signal of 1V at 28.75MHz. We modified the model constants to accommodate a low frequency pulse signal. We targeted that time because we intended to use the memcapacitive device as a biologically plausible artificial synapse [39, 43]. After a complete cycle, reset pulses were applied to reset the output of a gate before a new cycle began.

Figure 6: Timing diagrams of the 3-input AND gates (Sheridan memristive gate and Biolek memcapacitive gate). Each pulse was long. The bit values (0’s and 1’s) were added to show the input combinations of , and . is the output of the memristive gate and is the output of the memcapacitive gate.

Since a mem-device inverter cannot be built, we used CMOS inverters to build NAND, NOR, and XOR gates. For the full adder mem-device circuits, we utilized the mem-CMOS hybrid design of Cho et al. [8]. Their results showed that multilayer memristor-MOS circuits can implement any basic logic gate, such as AND, OR, NAND, NOR, and XOR.

Fig. 6 shows the timing diagram of the 3-input mem-device AND gates. The bit values (0’s and 1’s) were added to show all input combinations. and show the outputs for the memristor and the memcapacitor gate respectively. Similar to memristive gates, our memcapacitive gates also showed dynamic hazards, a common phenomenon for memristive gates [26]. Dynamic hazards occurred when the mem-devices switched their internal state (from and vice versa). Within these transition times, the output logic was undefined.

Figure 7: Dynamic logic hazards of 3-input memcapacitive AND(-) and NOR(–) gates using the Biolek model. The inset shows the output values in the interval []. With a pulse, the spike width of a logic hazard was about for the memcapacitive AND gate and about for the memcapacitive NOR gate.

The inset in Fig. 7 shows a dynamic hazard of the memcapacitive AND and NOR gates in the interval . The spike width estimates were and about for AND and NOR gates respectively. With a pulse width of , dynamic hazards can be potentially avoided by adding a time delay before reading the outputs. Another approach to remove dynamic hazards is to add buffers or inverters along the signal paths to restore the logic signals [26].

Figure 8: Power consumption of the mem-device logic and CMOS gates. The Biolek and Mohamed gates are memcapacitive gates, the rest are memristive gates. The overall winners for the mem-device gates were the Mohamed memcapacitive gates.

Fig. 8 shows the power consumptions for the mem-device gates as well as for 32nm CMOS gates. The power consumption was determined with SPICE by using RMS measurements of voltages and currents over a complete cycle of pulses (where is the number of inputs of a gate). For AND and OR gates, the Sheridan memristive gates consumed less power than the Biolek memcapacitive gates. The overall winners were the Mohamed memcapacitive gates. Furthermore, the Sheridan memristive gates required a 4.8V pulse amplitude whereas the memcapacitive gates only needed 2.4V. A lower voltage can be an advantage for interfacing with CMOS devices that are operated in a low-power mode [10].

The memcapacitive circuits outperformed the memristive circuits in terms of power consumption for XOR and FA. Compared to CMOS gates, the Mohamed memcapacitive AND and OR gates used less power. The memcapacitive XOR and full adder circuits, however, used more power than CMOS circuits due the CMOS inverters that are needed to implement NOT functions. In fact, the power consumptions of the CMOS inverters for the mem-device XOR and full adder circuits contributed about to the total power consumptions.


max width=

Table 2: Summary of mem-device gates’ power consumption. Logic pulses of and were applied to simulate all input combinations. CMOS inverters were used for the mem-based NAND, NOR, XOR, and FAs.

Table 2 summarizes the results of our simulations. CMOS inverters were used for the mem-based NAND, NOR, XOR, and FAs. We compared the average power consumptions of the memristive gates (Chang, Oblea, and Sheridan) and the CMOS gates with those of the Mohamed memcapacitive gates (the overall winners) for power saving factors. The results of the power saving factors are shown in Table 3.

Gate Chang Oblea Sheridan CMOS
MemR MemR MemR 32nm
Table 3: Power saving factors when comparing the average power consumptions of the memristive gates and the CMOS gates with those of the Mohamed memcapacitive gates.

These results show that memcapacitive gates are a promising option for implementing low-power digital logic circuits.

4.2 Mem-devices in Crossbar Classifiers

A classifier often functions as an output layer, for example in deep learning networks for image processing and pattern recognition. In a pattern recognition application, a classifier is trained in a supervised way, in which expected outputs are provided along with the input images. Once the training process is completed, the classifier is tested with a different set of image data for how well it can recognize similar patterns. We trained and tested our mem-device crossbar classifiers with two typical datasets: MNIST [11] and CIFAR-10 [27]. The MNIST dataset contains handwritten digits of size . This dataset has 60,000 training and 10,000 testing images. The CIFAR-10 dataset is a collection of 60,000 color images of size of , which is divided into 50,000 training and 10,000 testing images. There are 10 different classes of objects.

Figure 9: An example of an artificial network that performs image recognition.

Fig. 9 shows an example of a network performing pattern recognition that we employed for training and testing our memcapacitive classifiers. In this network, training and testing images are divided into smaller patches of pixel values. The converter then converts image pixels into input values for the coder. The coder encodes the pixel inputs, aggregates these inputs into higher-order features of input images, and produces input vectors for training and testing the classifiers.

We first trained the mem-device crossbar classifiers and then tested the classification performance. We also calculated the average power consumption per image for both the training and testing phases.

Figure 10: Classification performance and power consumption of the mem-device classifiers for the MNIST dataset. The power measurements do not include the power consumption of the virtual ground modules.

The training stage of a classifier, particularly a mem-device crossbar classifier, was composed of two phases: the inference phase and the update phase. In the inference phase, the outputs of the classifier were collected with applied training data while the internal states of mem-devices remained unchanged. We normalized the input vectors to ensure that the input voltages were less than the threshold voltages for the mem-devices and that the mem-devices did not change their internal states during the inference phase. In the update phase each mem-device was updated individually based on the feedback from a supervised learner. The supervised learner used gradient descent with back-propagation to determine how to update each mem-device with a pulse. The pulse is specific to the Chang memristive device and we used it for all classifiers. Once the classifiers were trained, they were tested with test images for clarifications. Both the training and testing stages were performed in Python. The average power was determined as the average power consumed by all mem-devices during the inference phase, the update phase, and the testing phase.

Figure 11: Classification performance and power consumption of the mem-device classifiers for the CIFAR-10 dataset. The power measurements do not include the power consumption of the virtual ground modules.

Fig. 10 shows the simulation results of the mem-device classifiers for the MNIST dataset. The mem-device crossbar had a size of . The classifier size was determined by the input image vectors. These vectors were generated by the sparse and independent local network (SAILnet) algorithm for the MNIST dataset, which has patches with over-completeness of 2. SAILnet utilized an improved model to represent a more realistic response of a mammalian visual cortex [61]. The results show that our memcapacitive classifiers performed similarly compared to the memristive classifiers while they consumed less power per image on average. As one can see, the Biolek memcapacitive classifier has the lowest power consumption of all models.

Fig. 11 compares the simulation results of the mem-device classifiers for the CIFAR-10 dataset. In order to maintain a reasonable size of our mem-device classifiers (such as ), the color images were converted to gray scale images for training and testing. Furthermore, a whitening process was applied to the input images in order to reduce the highly correlated adjacent pixels, which showed to improve both the training time and performance [14]. The length of each input image vector determined the size of the classifiers. For CIFAR-10, the SAILnet algorithm generated the input vectors of patches and an over-completeness of 2.

As one can see from Fig. 11, the memcapacitive classifiers did not reach the performance of memristive classifiers, but they consumed less power. The performance of memcapacitive classifiers correlated directly with the setting parameters (the learning rate , the update pulse width , the update pulse amplitude , and the offset voltage ) during the training phase. These parameters were chosen based on experiments.

We suspect that the memcapacitive classifiers do not reach the performance of the memristive classifiers for the following reason: since we do not have positive and negative weights, is used to so that weight is set between and after a training phase. If is low, most weights are bound to . If is high, most weights are set to . For the MNIST dataset, the inputs are very sparse and we can, therefore, find a reasonably good value of experimentally. On the other hand, the inputs of the CIFAR-10 dataset are not sparse enough. As a result, a small change in causes the entire weight matrix to be shifted to either or . The memristive classifiers seem to be less sensitive to the value, and, therefore, perform better.


max width= Model Device Dataset MNIST CIFAR-10 Type Perf. Crossbar Perf. Crossbar (%) ) (%) Chang [6] Oblea [31] Biolek [4] Mohamed[29]

Table 4: Summary of the classification performance and power consumption. The power measurements do not include the power consumption of the virtual ground modules. The power measurements were averaged over each image for both the training and testing phases.

Table 4 shows a summary of the simulation results. Using the average power consumption of the Biolek memcapacitive classifier as a reference, we compared its results with those of the Chang and Oblea classifiers. For the MNIST dataset, the Biolek classifier could achieve equal classification performance and save power by factors of and respectively. For the CIFAR-10 dataset, the Biolek classifier saved power by factors of and .

5 Discussion

As it was shown in Table 1, the Oblea device has the slowest settling time with the exception of the Mohamed device. As a result, we used pulses to test all mem-device logic gates. Operating mem-device logic gates with pulses is quite slow compared to CMOS logic gates. However, the Biolek memcapacitive logic gates with a smaller switching time are capable to operate with pulses.

Both memristive and memcapacitive gates suffered the effect of dynamic hazards. Dynamic hazards occurred when the mem-devices of a gate switched their internal states. Therefore, a delay time was required before the gate’s output could be read. This delay time is similar to the setup time in a CMOS gate, although the CMOS setup time is much smaller. Recent studies have shown that new memristive devices can switch their internal states much faster (in the range of ns and ps) [21, 9]. A faster switching time would imply less dynamic hazards.

The Mohamed memcapacitive XOR and the full adder circuits did not outperform the CMOS circuits in terms of power consumption. However, about of the power consumption was due to the CMOS inverters and transistors that are required for the gates in addition to the mem-devices.

The performance of the memcapacitive classifiers depends on how the memcapacitive devices are updated. The process involves setting four parameters: the learning rate , the update pulse width , the update pulse amplitude , and the offset voltage . These parameters were based on experiments. A systematic exploration of the parameter space is beyond the scope of this paper. We expect that the classification performance can be further increased with better parameters.

Moreover, virtual ground modules played an essential role in alleviating the effect of sneak-path currents within the crossbar networks. We have left out the power figures for these modules because they are highly technology-dependent.

6 Conclusion

Our work has shown that low-power memcapacitive logic circuits can be implemented. The memcapacitive gates consumed about less power compared to memristive logic gates. The lack of a mem-inverter makes the possible logical basis incomplete. The inverter operation, by its nature, requires an active element to reverse its input signal, which cannot be realized by passive mem-devices. Used for classifiers, memcapacitive devices were shown to reduce the power consumption by a factor of for MNIST and a factor of for CIFAR-10. For the classifier, we relied on virtual ground modules, which remove the effects of sneak-path currents, but consume significant power. Finding other options to eliminate sneak-path currents without the need of virtual ground modules could further lower the power consumption.

7 Acknowledgments

This work was supported by the Defense Advanced Research Projects Agency (DARPA) under award # HR0011-13-2-0015. The views expressed are those of the author(s) and do not reflect the official policy or position of the Department of Defense or the U.S. Government. Approved for Public Release, Distribution Unlimited.

The authors also thank Jens Bürger and Walt Woods for the helpful discussions.


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