Mapping of Topological Quantum Circuits to Physical Hardware
Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.
Quantum computing is at a pivotal point in development. The major enabling factor is the greatly enhanced understanding of highly efficient quantum error-correcting codes which allow reliable operation of a quantum computer even when its individual qubits have very large error-rate. This paper focuses on the generic class of measurement-based topological quantum computers Dennis et al. (2002); Fowler et al. (2009); Raussendorf et al. (2007); Fowler & Goyal (2009) (TQC), which combine several advantages that make them one of the most promising paradigms to build scalable quantum computers in the near future Stock & James (2009); Devitt et al. (2009); Meter et al. (2010); Jones et al. (2012); Yao et al. (2012); Ladd et al. (2010); Ghosh et.al (2013); Nemoto et.al (2013); Fowler et.al (2012). TQC is based on advanced topological quantum error-correcting codes, where the quantum hardware produces a well defined array of qubits that are arranged and connected using quantum entanglement links in a regular 3D lattice.
TQC allows, in principle, a reliable realisation of large quantum algorithms, such as the Shor algorithm to factor numbers in polynomial time Shor (1997); Devitt et al. (2012), a task that is not efficiently possible on a classical computer. However, implementing complex functionality requires specific design flows based on clear abstraction levels and automated synthesis steps. In case of classical circuits, the design stack typically includes algorithmic level, register-transfer level, gate level, transistor level, and mask level (sometimes, more levels are defined). In over 50 years of classical circuit design, a large variety of automated and semi-automated methods to translate a design from a higher level to a lower level have been developed.
For quantum algorithms based on the TQC paradigm, a design stack can also be defined (Figure 1). A quantum algorithm, such as the Shor algorithm, is first transformed into a quantum circuit consisting of quantum gates (each gate is a manipulation of typically 1, 2 or 3 qubits that can be described by a unitary matrix). This step is required for TQC and all other quantum architectures, and substantial body of work on gate-level design and optimisation has been published both in Quantum Physics and in Computer Engineering community Bullock & Markov (2004); Shende et al. (2006); Whitney et al. (2007); van Dam et al. (2007); Maslov et al. (2008); Patel et al. (2008); Amy et al. (2012).
TQC circuits allow for a generic geometric description that abstracts from details, in particular the underlying error correction, which is sufficient to capture relevant algorithmic interactions. The geometric structures in the TQC circuit, representing encoded qubits and encoded gates are embedded (via physical qubit measurements) within the physical 3-dimensional lattice. The model provides direct support for only a restricted subset of quantum operations, due to symmetries necessary for error correction to function, and if the high level circuit contains arbitrary gates, they must first be mapped to the supported operations using a series of well-known steps Bravyi & Kitaev (2005); Dawson & Nielsen (2006); Devitt et al. (2012). After that, the circuit can be translated into its canonical geometric representation where each gate has a corresponding region of the 3D lattice where it is implemented. The first automated optimisation method for a restricted case of two-dimensional descriptions was presented in Paler et al. (2012).
This paper focuses on the next synthesis step: mapping of the geometric description to the physical level. The output of the mapping consists of two parts: A direct instruction set for the quantum hardware and a classical instruction set for data processing. The geometric description of the TQC circuit specifies a layout of how logical qubits should be arranged within the lattice of physical qubits. The physical size and separation of these structures is proportional to the error correction strength needed for computation. TQC operates by performing measurements on physical qubits within the lattice. The type of measurement depends on whether a given physical qubits is inside or outside the geometric region defining a logical qubit. The instruction set for the quantum hardware consists of translating the geometric structure to a specific set of individual measurement instructions for the physical qubits in the lattice.
The classical data processing information is also required for byproduct calculation. Within a TQC circuit, large sets of physical qubits form what is known as a correlation surface. These sets connect the inputs of a quantum circuit to the outputs. The overall parity of these correlation surfaces (when they are measured) tells us how the logical information must be corrected in order to successfully propagate from input to output. The classical control software of a TQC must know these structures in order to successfully operate. Therefore, for a TQC circuit specification, the determination of the physical qubit sets that define correlation surfaces and how they interact is non-trivial and constitutes the by far most complex part of the mapping algorithm.
The result of the mapping algorithm is a 3D lattice of qubits along with instructions how to use it. This is vaguely related to the general-purpose hardware and the customised software of a classical microprocessor. Note that TQC is technology-independent: any implementation where qubits can be arranged in two or three dimensions can be used to realise this model Devitt et al. (2009); Yao et al. (2012); Jones et al. (2012). Therefore, our work closes the gap between the high-level synthesis (which reaches up the geometric description level) and technology-oriented physical implementation approaches. It is the foundation for the first complete automated flow from the quantum algorithm to the implementation.
The physical qubits are arranged in a large three-dimensional lattice and are entangled to form a single, massive, universal quantum state. A universal state is a specific quantum state that can be used to implement any fault-tolerant quantum algorithm via measurement of each qubit in the state Raussendorf et al. (2003). The unit cell of the lattice is illustrated in Fig. 2a). Prior to actual computation, each qubit is initialised in the superposition state, . Once all qubits are initialised, a two-qubit gate is used to entangle any two qubits that are connected in the lattice with an edge. The unit cell is the building block of the lattice, and its structure is repeated along three dimensions, which are denoted by (width), (height) and (time). TQC is implemented via sequential measurement of a 2D cross section of the full 3D lattice. Information is propagated along the third axis of the lattice via the entanglement links, with processing occurring during these teleportation steps. Hence the third dimension of the physical lattice is identified with the temporal axis (-axis).
One general unit cell of the lattice has 27 () vertex positions, 18 of which are occupied by physical qubits, denoted by gray and black circles in Figure 2a). A lattice with unit cells has a total of positions, because neighboring cells share a side. All physical qubits in the complete lattice form the set . The positions not occupied by qubits form the set . A position must be the center of a unit cell. The physical qubits at the faces of such a cell (six gray circles in Figure 2a) are denoted by , and the qubits at the sides (12 black circles in Figure 2a) are denoted by . The set of all qubits of a cell is . Note that is the union of these sets for all the cells in the lattice.
The topological lattice contains two self-similar lattices that are interlaced (see Figure 2b)). The primal lattice (with corresponding ) contains all the cells having odd coordinates, and the dual lattice (with corresponding ) contains all the cells having even coordinates. If eight dual cells of the lattice are arranged into a cube, then a primal cell exists at the intersection point, and therefore the set of all physical qubit coordinates in the lattice can be expressed as .
Physical qubits (organised in cells arranged in a 3D-lattice, as described above) are used to encode logical qubits. The underlying lattice is a computational resource for the logical layer, similar to how the hardware is a computational resource for the physical layer. However, at the logical layer, all operations are error-corrected, implying that logical qubits are initialised, operated on and measured using logical operations. It should be noted that the logical information is not decoded prior to any logical operation and afterwards re-encoded; operations are applied directly on encoded physical qubit states. Valid operations within the logical space are designed specifically such that physical errors do not cascade to cause uncorrectable faults. Therefore, the TQC model is known as a fault-tolerant model of quantum computation.
The geometric structures, which define encoded qubits, are created by measuring relevant physical qubits in the basis ( states). This effectively creates a hole in the lattice, known as a defect. It is the defects that encode information. Two types of logical qubits can be defined depending in which of the lattices the measurements of physical qubits are performed and consequently where defects are created. The physical qubits sets and represent the physical qubits that are internal to defects which are measured in the basis, with and . Primal defects are created by measuring qubits in the set and Dual defects are created by measuring qubits in the set .
Figure 3 illustrates the structure of two defects which encode a single logical qubit (the unit cells that are not relevant for the defects are not shown). In this structure a temporal axis is defined running from the front of the structure to the rear and this encoded qubit is undergoing a simple identity operation. i.e. the input of this topological circuit starts on the 2D layer at the front of the image and via measurement is teleported to the 2D layer at the rear. There are three sets of physical qubits that are relevant for the mapping. One is the sets that are used to define primal (dual) defects. These qubits are illustrated in Figure 3 as green circles and are measured in the basis to simply remove them from the lattice. The second set are known as logic operators. Logic operators are sets of physical qubits whose parity determine the logic state of the encoded information. Two types of logic operators exist, one is a loop operator that completely encircle an encoded defect. The second is a chain that connects both defects (illustrated by orange squares in Figure 3b)).
For primal (dual) defects, the loop operators correspond to the logical () operator while the chain corresponds to the logical () operator. The final set of relevant qubits are illustrated as blue triangles in Figure 3. These sets are known as correlation surfaces. The correlation surface connects logic operators from an input layer in the cluster to an output layer. The ring and chain operators need to be connected from the input layer (front of the image) to the output (rear of the image). The qubits illustrated in blue perform this operation. If each qubit in blue is measured in the state ( basis) we connect the chain (ring) operators from the input side to the chain (ring) operators on the output side. If we wished to measure the logical state, by measuring and calculating the parity of the logical operator we would measure each physical qubit in the basis. By measuring these qubits in the basis instead, the logical information is teleported to the next layer in the lattice, with a correction that is determined by the parity of the basis measurements. The correlation surfaces form either sheets or tubes. For primal (dual) defects, sheets are the logical () surfaces and tubes are the logical () surfaces. In order to track information as it moves through the lattice, we need to know which qubits are associated with these surfaces, as the parity of these measurements will dictate the correction that needs to be applied to encoded information as it moves through the lattice.
The primary goal of this work is, given a geometric definition of a TQC circuit, to determine the information needed by the (classical) control software of a quantum computer in order to operate TQC hardware that implements a circuit. This information includes the measurement basis of the physical qubits. In Figure 3, the solid circle qubits (defect-internal) are measured in basis whereas the triangle qubits (correlation surfaces), square qubits (input/output) and white qubits (qubits for error correction) are measured in basis. Moreover, the measurement outcomes for qubits in correlation surfaces are needed to calculate corrections to encoded data as they propagate through more complicated topological structures that are not considered here. Therefore, the mapping procedure must identify the physical qubits for each correlation surface ( and ).
Other geometric structures, corresponding to specific logic operations, are shown in Figure 3c). For a primal pair of defects, the horseshoe structure corresponds to initialising a qubit in the state, the pair of parallel defects correspond to initialisation in the state and the third structure corresponds to state injection. State injection allows us to introduce an arbitrary state into the TQC lattice by measuring a single physical qubit that exists at the vertices of the pyramid structure. State injection is instrumental in the TQC model to achieve universal computation Bravyi & Kitaev (2005); Raussendorf et al. (2007). In Figure 3c) the temporal axis runs from left to right. In order to perform logical measurement, we use the exactly same structures, but in the reverse temporal direction (this allows for measurement in the and basis, i.e. and bases). The regions that are marked as grey and green correspond to the sets of physical qubits whose parity defines the parity of the initial encoded qubits.
The concept of state injection in the topological model is instrumental for achieving universality. The power of quantum computation is intricately related to the introduction of these injected states and their consumption to realise non-Clifford gates through teleportation. However, in the context of this mapping algorithm, there is essentially no difference in the classical computation associated with the geometric structures in Fig. 3c). While the right most structure in Fig. 3c) represents the injection of a non-trivial encoded state, the sets of physical qubits that define byproduct operators for this newly created state are no more complex to calculate than the sets associated with standard Clifford initialisation. Therefore, the introduction of injected logical states and the realisation of non-Clifford gates in a topological circuit poses no complexity problem for the mapping algorithm.
The mapping problem of a TQC circuit is the accurate determination of physical qubits in the topological lattice corresponding to relevant correlation surfaces that define the operation of the circuit. The input to this algorithm is a suitably optimised topological circuit that is compatible with the error-corrected model and hence the underlying computational hardware. Algorithmic constraints at both the physical and logical level have already been taken into account via the construction and optimisation of the input circuit. Before formally introducing the problem, we illustrate it through the example of a cnot operation implemented via a braid operation between two encoded defects (Figure 4). A correlation surface that begins on primal defects cannot terminate on dual defects and vice versa. Therefore, as defects are braided, a correlation surface extends around the qubit involved in the braid. It is this interaction that entangles the logical qubits.
Figure 4 illustrates how correlation surfaces are defined, using the shorthand notation that is illustrated in the inserts of Figures 3a) and b). In Figure 4b) we show the correlation surface (sheet) on the control qubit (a dual type defect). Due to a braid with a primal defect, this correlation surface must extrude around the second defect and forms a tube. This correlates the outputs of the two qubits when the control qubit is in an -basis eigenstate. Figure 4c) shows the correlation surface (tube) on the control qubit. Here, the surface is not perturbed by the braid. Therefore the output remains uncorrelated when the control is in a -basis eigenstate. This circuit correlates output qubits in precisely the way needed to realise a CNOT operation Nielsen & Chuang (2000); Fowler & Goyal (2009).
These surfaces are not specified with the TQC circuit, and therefore the mapping procedure must derive them from the geometric structure and map them to the actual set of qubits that are used in the lattice such that they can be tracked as the circuit is implemented.
Problem Formalism. The mapping procedure takes a geometric description of a TQC computation as input and calculates a data structure which contains the required information of each logical qubit. Each logical qubit in is specified by a set, , of directed segments, given by their end points . Recall that is the set of lattice coordinates that are not occupied by qubits and can be centres of unit cells. Each segment has one of six possible directions . To convert to , an intermediate representation where each logical qubit is described by a directed, cyclical graph, is calculated first and then used to derive .
Geometric Description and Representation by Graphs: For each logical qubit , a directed cyclical graph is defined. The set of possible graph vertices contains representations of unit cells from set . There is a bijective mapping between and : yields the three () lattice coordinates of the cell corresponding to . represents the end points of the segments in , and represents the connections between the end points. A graphical example for this construction is offered in Figure 3c).
Mapping Algorithm. Representation of Logical Qubits by Set Tuples: The tuple representation of a logical qubit contains all the information which is needed to implement it and its interactions with other qubits on a quantum computer. The ultimate outcome of the mapping procedure described next is the set which contains tuples for all logical qubits .
The specifics of the mapping algorithm can be found in the Methods section. The edges in form a Hamiltonian path, containing all vertices from . During the mapping, the path can be either modified by that removes vertex and its incident edges, and creates a new edge between its neighbours, or the function that deletes the edge, and creates the new edges and .
Within , stands for the type of the logical qubit (primal or dual). includes all defect-internal physical qubits (i.e., those to be measured in the basis, whereas all other qubits will be measured in the basis). and are physical qubits that define inputs and outputs, respectively. In Fig. 3, the qubits in were shown in green and the qubits in and in orange. Sets and include all physical qubits that are part of the and correlation surface, respectively. Finally, is the set of injection points. Note that the primal (dual) qubits are defined using coordinates on primal (dual) cells.
As mentioned earlier, the correlation surface is a sheet for a primal logical qubit and a tube for a dual logical qubit. The correlation surface is a tube for a primal logical qubit and a sheet for a dual logical qubit. For convenience, we introduce functions which returns for primal logical qubits and for dual logical qubits and which returns the corresponding tube in a similar way.
Mapping Examples. The presented algorithms were implemented and their execution will be illustrated by examples. The example from Figure 5 illustrates how a complete sheet is computed. A more complex example, for the computation of tubes and sheets, is presented in Figure 6, and procedure starts from the TQC computation described by the geometry presented in subfigure a). The circuit consists of 3 logical CNOTs performed between 4 logical qubits: 3 primals (the qubits ) and a dual (qubit ). The circuit will implement the following sequence: , , .
The quantum circuit in Figure 6a) is converted to a geometric form appropriate for the TQC model (Figure 6b)). The mapping will first determine the tube surfaces of each logical qubit and the results shown in Figure 6c) will be obtained. Figure 6d) contains the result of the physical qubit sets forming sheet surfaces. For the same dual logical qubit (the third qubit in Figure 6a)) all the intermediate steps of the sheet computation are graphically presented in Figure 6e) .
Algorithmic Complexity: The algorithmic complexity of the mapping procedure is analysed in the following. For the computation of all the qubit sets, computed by the algorithm in Eqn. 1, the mapping procedure requires a single qubit-cycle traversal, while the computation of the coordinates is straightforward (see the illustration presented in Figure 3a and the corresponding legend). Therefore, for a given logical qubit , the runtime complexity is linear in the number of vertices () of the graph-cycle representing the geometry.
For the runtime complexity analysis of the sheet mapping procedure a worst-case geometry has to be defined. Such a geometry, when mapped in the 3D, will have to require a maximum number of reshape-rule applications in order to be able to compute the corresponding sub-sheets. The search of a geometry will consider that the algorithm from Eqn. 3 randomly selects a vertex from the cycle-graph (Line 1), and that the vertex is used as a pivot for the reshape-operation. These assumptions imply, that even after a sequence of operations is applied, there is no possibility to find a sub-sheet and to reduce the number of vertices, and thus a further is necessary. For a graph with vertices, a worst-case situation arises when vertices are arranged in a pattern similar to the one in Figure 7, where the red cube indicates the vertex and the cycle is traversed clockwise. The graph vertices (where edges are joined) are not represented.
After a first traversal of the graph, the reduce operation could not have been applied, and a followed by corresponding operations will transform the graph like in the right panel of Figure 7. It can be noticed, that until the step-like construction is not reshaped, no can be applied. However, after each , co-linear vertices can be , thus minimising . Overall, the complexity of the sheet-finding procedure is bounded by .
While the mapping algorithm itself scales polynomially with the size of the cycle graph, we cannot make any claims regarding the size of the cycle graph given an optimised topological circuit. The size of the cycle graph is essentially related to the number of 90 ”pivots” made by defects in the topological circuit we do not know yet how big, in general, this set is for a given circuit specification. Current methods in systematic optimisation for topological circuits are still in their infancy Paetznick & Fowler (2012) and determining the scaling of the number of these pivots for a given number of logical qubits is unknown. However, the physical size of the topological circuit (in terms of the physical volume of cluster needed to implement the circuit at a fixed error correction strength) has marginal influence on the scaling of the mapping algorithm itself. Instead, the scaling of the mapping algorithm will be dominated by the total number of pivots made by the input circuit specification.
Correctness: Checking the correctness of the algorithms, implies verifying their termination and the fact that the correct physical qubit coordinates are computed. Again, for the algorithm in Eqn. 1, the termination is guaranteed because a single traversal of the cycle-graph is necessary. The correctness of the computed coordinates is shown by comparing the algorithm instructions with Figure 3. The direction (Line 4) is associated with the green line in the figure, where and are the coordinates of the edge vertices. For example, let us consider that the two cells from the lower defect are and . This implies, that by selecting the two neighbouring coordinates (Line 7), the co-ordinates of the green marked qubits (the defect set ) is computed. The remaining qubits (Line 8) that do not belong to are the light blue marked qubits, which are associated with the tube correlation surface that surrounds the defect region. One has to note, that for defects with a cross-section larger than a cluster-cell, the set union operations on Line 10 and Line 12 are to be interpreted as , meaning that if element existed in the set it will be removed, otherwise it will be included.
The termination of the sheet-finding algorithm (Eqn. 3) can be illustrated by starting from the fact that the geometric description is mapped into a 3D representation where only 6 segment directions are possible (see the discussion of the and rules). A geometrically described defect configuration of a logical qubit (in the absence of any possibility to apply or ) will have an even number of edges in its associated graph. Considering all the worst-case geometries (an example is Figure 7), it can be seen that after a graph-traversal, either or (followed by ) can be be applied. The number of maximum consecutive is bounded by . Thus, the number of graph-vertices is continuously reduced, and the termination of the algorithm is guaranteed.
The correctness of the coordinates computed from the sub-sheets is shown by comparing the Lines 3 and 4 of Eqn. with Figure 3b). For a logical qubit of type , the set of all possible side qubits (depicted gray in Figure 2 for a single cell) is . For the two defects from Figure 3b) the instruction on Line 3 will return the coordinates of both the orange and the blue marked qubits, which intersected with will return only the blue qubits. These are the ones necessary for the computation of a sub-sheet. If two sub-sheets overlap (which is possible, given the way the algorithm in Eqn. functions), then the intersection set is not part of the set of qubits defining the complete sheet of a logical qubit (Line 4).
A final detail that needs explanation is that the approach, by finding sub-sheets, is correct. Initially, one has to consider that for TQC, by deforming the defect geometries, does not change the computation, because the topology of the description is relevant, and not its geometry. For this reason, for each individual logical qubit described as a graph, the operation is valid, because the sheets of two topologically equivalent geometries will differ only in sub-sheet. For example, in the last panel of Figure 8b), the subsheet is the difference between the equivalent geometries: before and after applying the operation.
Another fact about the correctness of sub-sheet-finding appears when one considers the example presented in Figure 8a). Let us consider, the three qubits . Deforming the defect implies, that the qubits are not part of the defect anymore, and that are parts of the new boundary. This is equivalent to stating that the sub-sheet containing the qubits was created, and that after the change the complete sheet will contain .
It should be noted that the correctness of the mapping algorithm already assumes that the given topological circuit has been verified with respect to the initial circuit specification. In general, a compressed topological circuit may bare little resemblance to the original un-optimised circuit. Before a topological circuit is input to the mapping algorithm, we assume that it has been verified against the initial specification and consequently the qubits sets generated from the mapping algorithm will faithfully realise the original circuit when implemented in hardware. Optimisation of topological circuits may employ a technique known as bridge compression Fowler & Devitt (2012) which connects closed loop topological structures together. The algorithm detailed in this work is not currently designed to handle circuits containing bridged components, however modifying the algorithm to process arbitrary structures will be possible as arbitrary geometric shapes can still be decomposed into simple cycle-graphs. These modifications are the subject of future work.
In this paper we presented the first mapping algorithm that translates a topological quantum circuit into the specific measurement patterns required by the quantum hardware. We have also illustrated the necessary algorithm for the construction of correlation surface needed to appropriately track information as it propagates through the circuit. The mapping of a topological circuit specification to the physical measurements in the lattice is one of many classical components necessary for realisation of quantum circuits. This classical library consists of both office and online components. Offline software processing consists of the compilation and optimisation of a topological quantum circuit Devitt et al. (2012); Paetznick & Fowler (2012); Fowler & Devitt (2012) and the mapping of this structure to the physical lattice. Online classical processing relates to the real-time decoding and processing of error correction data using algorithms such as minimum weight perfect matching Fowler (2013) and renormalisation group techniques Duclos & Poulin (2010). Ultimately, all classical processing will need to be integrated together to form a complete software package for controlling topological quantum computers.
This work is not only a necessity for the future operation of topologically protected quantum computation, but it is also a requirement for appropriate verification packages for topological circuit synthesis. The accurate construction of correlation surfaces allow us to compare the operation of a topological circuit against the abstract quantum circuit it is derived from. This is important as optimisation techniques for topological quantum circuits often result in structures that bare little resemblance to the original circuit specification. The further development of verification protocols is the focus of future work.
The Mapping Procedure. The algorithms to compute the classical control information are presented in detail in this section. For this purpose, we first describe several functions to translate information between the geometric description, the cycle-graphs and the tuple representation of logical qubits.
Function returns the type of a geometric segment that was translated into a graph edge. The segment type is used after physical qubits associated with the segment have been calculated in order to decide which set from they belong to.
Function takes and the segment type as inputs and returns the corresponding coordinate set of physical qubits that belongs to segments of with the specified type. For example, physical qubits from a segment of type it will be added to the set , and for segments the is returned.
Function yields the lattice-direction of the segment represented by the given edge. A further function is used to indicate the -th neighbour of vertex in the direction of the Hamiltonian path.
Function returns the vector representing the lattice coordinates of a graph vertex . The inverse function is used to infer the vertex given the lattice coordinates.
The function ; returns vertex mirrored at the line through its predecessor and successor in the cycle-graph, while the returns either or depending which is closer to vertex .
The mapping starts by constructing for each geometrical description of a logical qubit from the cycle-graph . Then, the corresponding tuple is initialised by setting to primal or dual according to the desired type and .
Sets are constructed by the algorithm shown in Eqn. 1. Recall that is either or , depending on whether is primal () or dual (). The algorithm traverses the cycle-graph . The lattice-direction associated with each edge of the graph is computed. For each cell of a segment, is its complete set of physical face qubits (see Section Results). Two face qubits along the segment are defect-internal and added to . The remaining four qubits are part of the tube correlation surface and added to set that is then added to . Coordinates of injection points are always found at the middle of the segment (Line 15). The coordinates of the qubits on segments are added to the corresponding sets and as given by at Line 12;
The sheet surfaces of each are found by a procedure that iteratively reduces the graph until it consists of just two vertices. The procedure constructs a sheet by finding one sub-sheet in each iteration, where a sub-sheet contains physical qubits bounded by a rectangle in either , or plane. Each sub-sheet is specified by two points where define the diagonal of the rectangle and have one equal component. Sub-sheets found by the procedure in different steps are disjoint, and the union of all found sub-sheets is the complete sheet. Figure 6d) illustrates a complete sheet composed of sub-sheets, and Figure 6e) shows the progressive calculation of sub-sheets (both figures will be discussed in more detail later).
The procedure transforms the graph by eliminating or moving vertices, while sub-sheets are calculated. Without giving a full formal proof for correctness of these transformations (such a proof will require advanced quantum computing concepts which are out of this paper’s scope), we illustrate the modification of a sheet boundary in Figure 8. The dashed line in the figure is indicating the direction of one defect involved in generating the sheet surface . By changing the direction of the defect, the boundary is transformed into . In terms of sub-sheets, the sub-sheet is added after the change of defect direction.
The algorithm illustrated in Eqn. 3, used to compute the set of sub-sheets for each logical qubit, will remove vertices of the graph, by constantly traversing it (Lines 3, 20), until only vertices are left (Line 2). Eqn. 2 takes each set and constructs of each logical qubit tuple . For the subsheet the function constructs the set of coordinates able to represent physical qubits.
Considering the structure of the lattice and the way the geometrical descriptions are constructed, it can be noticed that the cycle-graphs have an even number of vertices. It should be also noted that the operation is not directly applied by the algorithm, and the number of vertices is modified only during the operation, or after the operations is applied.
The Reduce Operation: The algorithm illustrated in Eqn. 3 modifies the graph by applying the the operation. The path is reduced if for consecutive edges, the first and the second edge represent opposite associated directions into the lattice (Line 10). For example, in Figure 8b) this is the case for the edges , where and have opposite directions.
The operation is defined as the sequential application of:
We illustrate the reduce operation by applying it to vertices and of Figure 8b). The sets , , are constructed. Because and , the set is equal to and . After the vertices from are removed, no further vertices are inserted or removed because the corresponding sets are empty. However, for the example in Figure 8b) this is not the case as , thus effectively removing the vertex and inserting vertex .
The Reshape Operation: In order for the graph to be reduced, it may be required to represent an equivalent geometrical description. Thus, vertices are not removed or deleted, but moved ( remains constant). The operation is the sequential application of:
In the context of the algorithm in Eqn. 3, the function is called if during a complete graph traversal the operations could not be applied. For the example of Figure 8b), where is called, the resulting graph will be obtained by removing and inserting . Applying for a second time at the same position would undo the initial application, thus is the inverse of . Therefore, the pivot (Line 3), used for checking if a traversal completed (Line 20), is updated (Line 24).
The maximum number of cycle traversals is , when after each traversal a operation is required, while the number of consecutive operations is bounded by .
The number of vertices of the cycle-graph is initially even due to the shape properties of the geometrical descriptions. Moreover, it remains even during the execution of the algorithm. Operation eliminates exactly two vertices from the graph (set ), while the sets of further added and deleted vertices ( and , respectively) are always of the same size. Operation does not add or delete vertices. However, three consecutive vertices may represent a straight line after a operation, in which case they are replaced by two vertices (Line 14). It can be shown that one further vertex elimination must follow, keeping the overall number of vertices even.
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We thank A.G. Fowler for helpful discussions. S.J.D. and K.N. acknowledge support from the HAYAO NAKAYAMA Foundation for Science & Technology and Culture, the Quantum Cybernetics (MEXT) and FIRST projects, Japan. A.P. and I.P. acknowledge support from DFG project PO1220/3-1 and BAYFOR grant..
A.P. and S.J.D. conceived the idea. A.P. and I.P. were responsible for algorithmic simulations. S.J.D. and K.N. were responsible for results verification. All authors were responsible for drafting of the manuscript.
Correspondence and requests for materials should be addressed to A.P. (firstname.lastname@example.org).
Competing financial interests.
The authors declare no competing financial interests.