Low Complexity Full Duplex MIMO:
Novel Analog Cancellation Architectures and Transceiver Design
Abstract
Incorporating full duplex operation in Multiple Input Multiple Output (MIMO) systems provides the potential of boosting throughput performance. However, the hardware complexity of the analog selfinterference canceller in emerging full duplex MIMO designs mostly scales with the number of transmit and receive antennas, thus exploiting the benefits of analog cancellation becomes impractical for full duplex MIMO transceivers, even for moderate number of antennas. In this paper, we present two novel architectures for the analog canceller comprising of reduced number of cancellation elements, compared to the state of the art, and simple multiplexers for efficient signal routing among the transmit and receive radio frequency chains. One architecture is based on analog taps (tap refers to a line of fixed delay, variable phase shifter, and attenuator) and the other on AUXiliary (AUX) Transmitters (TXs) that locally generate the cancellation signal. In contrast to the available analog cancellation architectures, the values for each tap or each AUX TX and the configuration of the multiplexers are jointly designed with the digital transmit and receive beamforming filters according to certain performance objectives. Focusing on a narrowband flat fading channel model as an example, we present a general optimization framework for the joint design of analog selfinterference cancellation and digital beamforming. We also detail the sum rate optimization objective together with its derived solution for the latter architectural components. Representative computer simulation results demonstrate the superiority both in terms of hardware complexity and achievable performance of the proposed low complexity full duplex MIMO schemes over the lately available ones.
I Introduction
In band full duplex, also known shortly as Full Duplex (FD), is a candidate technology for fifth Generation (5G) wireless systems because of the potential spectral efficiency gains that can be achieved through simultaneous uplink and downlink communication within the entire frequency band [2, 3]. An FD radio can transmit and receive at the same time and same frequency resource unit, consequently, it can double the spectral efficiency achieved by a half duplex radio. Current wireless systems exploit Multiple Input Multiple Output (MIMO) communication, where increasing the number of transmit and receive antennas can increase the spatial Degrees of Freedom (DoF), hence boosting spectral efficiency. Combining FD with MIMO communication can provide further spectral efficiency gains [4, 5, 6, 7, 8, 9, 10]. Thus, enabling FD MIMO technology, for small to large antenna array systems, is of high interest in order to achieve the demanding throughput requirements of 5G wireless communication systems [11].
An FD radio suffers from Self Interference (SI), which is the signal transmitted by the FD radio Transmitter (TX) that leaks to the FD radio Receiver (RX). At the RX of the FD radio, the power of the SI signal can be many times stronger than the power of the received signal of interest (which is transmitted from another radio). Consequently, SI can severely degrade the reception of the signal of interest, and thus SI mitigation is required in order to maximize the spectral efficiency gain of the FD operation. As the number of antennas increases, mitigating SI becomes more challenging, since more antennas naturally result in more SI components. For the case of a Single Input Single Output (SISO) FD node, it has been demonstrated [12, 13] that significant SI mitigation can be achieved via a combination of analog and digital cancellation techniques, where an estimate of the received SI is subtracted from the received signal (which is the sum of the SI signal and signal of interest). A straightforward extension of SI mitigation solutions used in SISO FD to the case of MIMO FD can be envisioned. However, the hardware resources required for analog SI cancellation become the main bottleneck, since they scale with the number of antenna elements. Specifically, for the two most widely considered analog canceller solutions, which are: i) the architecture based on taps (a tap consists of analog components that implement delay, phase shift, and attenuation) [12, 14]; and ii) the architecture based on AUXiliary (AUX) TX Radio Frequency (RF) chains (a AUX TX RF chain generates an analog cancellation signal from an input digital reference signal) [13, 15], the hardware requirements in MIMO scenarios are as follows. For the case where the analog canceller is based on multiple taps, an extension to MIMO requires at least taps with and denoting the number of RX and TX antennas, respectively, at a FD MIMO node . For the case where the analog canceller is based on multiple AUX TX RF chains, an extension to MIMO requires at least AUX TXs. Consequently, depending on the number of TX and RX antennas at the FD MIMO node, the extension of SISO analog canceller solutions to the MIMO case may be prohibitively complex. Thus, recent works have proposed only digital SI mitigation for FD MIMO [4, 7]. These approaches exploit the availability of multiple antennas at the FD node in order to provide SI mitigation via digital BeamForming (BF); such an approach is known as spatial suppression. However, as has been pointed out, spatial suppression approaches often result in lower rates for both the outgoing and incoming signals of interest, since some of the available spatial DoF are solely devoted for mitigating SI.
In this paper we propose two novel architectures for analog SI cancellation and a novel optimization framework for jointly designing the analog canceller and the TX/RX digital BF parameters. The first new architecture for analog cancellation consists of multitap hardware, where the number of taps does not increase with the number of TX or RX antenna elements. The second new architecture includes AUX TX RF chains whose number does not depend on the number of TX or RX antennas. The number of taps in the one architecture and that of AUX TXs in the other can be chosen offline as a function of size constraints, cost per tap and cost per AUX TX RF chain, or other constraints on the analog canceller hardware. Both simplified analog canceller architectures are enabled via the use of MUltipleXers(MUXs) and DEMUltipleXers(DEMUXs), which allow flexible connectivity between the taps or AUX TXs and the transceiver antennas. The settings of taps or AUX TXs and the configurations of MUXs/DEMUXs is computed via our proposed optimization framework. The flexible signal routing via MUXs/DEMUXs enables the use of reduced taps or AUX TXs in an optimized way, since either of the latter will be used between the subset of TX and RX antennas where they are mostly beneficial. The digital beamformer and analog canceller parameters are thus designed by taking into account each others capabilities, hence the burden of SI mitigation is split between digital BF and analog cancellation. We note that the related work [4] has considered joint design of digital BF and analog cancellation, however these and related solutions [16, 17] assume underlying analog canceller hardware as in [12, 6, 14, 15, 13], which scales with the number of transceiver antennas. For the JointNull solution recently proposed in [18], although the number of analog cancellers does not necessarily scale with the number of antennas, the underlying architecture of the canceller (ie, number of taps or AUX TXs) is not taken into account in the BF design. As our simulation results will show, our proposed analog canceller architecture together with our novel joint design of analog cancellation and TX/RX digital BF is capable of achieving higher rates with less hardware compared to StateoftheArt (SotA) FD MIMO solutions. This paper’s contributions can be summarized as follows.

We present two novel analog SI canceller architectures, one based on multiple taps and another one consisting of multiple AUX TX RF chains. Both architectures include networks of MUXs/DEMUXs intended for efficient signal routing between either the taps or AUX TXs and the transceiver antennas.

We propose a general optimization framework for the joint design of analog SI cancellation and digital transceiver BF at FD MIMO nodes.

We present an example algorithmic design for the analog cancellation parameters as well as the digital TX precoder and RX combiner that targets at the maximization of the FD sum rate performance.

Extensive simulation results incorporating realistic models for nonideal hardware for both proposed analog canceller architectures are presented. We compare both designed low complexity FD MIMO schemes with lately available ones in terms of hardware complexity and achievable performance.
The outline of the paper is as follows. The considered system and signal models are included in Sec II, whereas Sec III presents our new analog canceller architectures. Our novel general optimization framework for FD MIMO operation is provided in Sec IV, and Sec V presents an example optimization problem together with a detailed low complexity solution. Simulation results are presented and discussed in Sec VI, while Sec VII concludes the paper and summarizes some future research directions.
Notation: Vectors and matrices are denoted by boldface lowercase and boldface capital letters, respectively. The transpose and Hermitian transpose of are denoted by and , respectively, and is the determinant of , while () is the identity matrix and ( and ) represents the matrix with all zeros. stands for the Euclidean norm of , operand represents the Hadamard entrywise product, and denotes a square diagonal matrix with ’s elements in its main diagonal. , , and represent ’s th element, th row, and th column, respectively, while denotes the th element of . and represent the real and complex number sets, respectively, is the expectation operator, and denotes the amplitude of a complex number.
Ii System and Signal Models
We consider a wireless communication system comprising of a FD MIMO node that wishes to communicate concurrently with a multiantenna node in the downlink and a multiantenna node in the uplink, as shown in Fig 1. We focus on investigating efficient FD operation at a single node, as such, we henceforth assume without loss of generality that nodes and operate in half duplex mode.
Suppose that the FD MIMO node in Fig 1 is equipped with TX antenna elements and RX antenna elements. Each antenna element is attached to a dedicated TX RF chain, similarly holds for the RX antenna elements and their respective RF chains. A TX RF chain consists of a Digital to Analog Converter (DAC), a mixer which upconverts the signal from baseband to RF, and a Power Amplifier (PA). An RX RF chain consists of a Low Noise Amplifier (LNA), a mixer which downconverts the signal from RF to baseband, and an Analog to Digital Converter (ADC). At the TX side, upsample and pulse shape processing are used to prepare the baseband signal for DAC sampling and RF transmission. At the RX side, a corresponding matched filter and downsampling is performed. The half duplex multiantenna nodes and are assumed to have and antennas, respectively, with each antenna connected to a respective RF chain.
For presentation clarity purposes, we assume narrowband flat fading channels for our signal model. Extensions for wideband frequency selective channels are left as future work. All nodes are considered capable of performing digital BF; for simplicity, we assume hereinafter that digital TX and RX BF at the focused FD MIMO node is realized with linear filters. In particular, we assume that node makes use of the precoding matrix for processing its unit power symbol vector (chosen from a discrete modulation set) before transmission. The dimension of satisfies , which complies with the available spatial DoF for the downlink MIMO channel. Similarly, node processes its unit power symbol vector (chosen again from a discrete modulation set) with a precoding matrix , where . Both the downlink and uplink transmissions are power limited according to and , respectively. Following the above definitions, the baseband received signal at node can be mathematically expressed as
(1) 
where is the downlink channel matrix (ie, between nodes and ), denotes the channel matrix for internode interference (ie, between nodes and ), and represents the additive white Gaussian noise (AWGN) vector at node with covariance matrix .
Upon signal reception at the FD MIMO node , analog SI cancellation is first applied to the signals received at its RX antenna elements before these signals enter to the RX RF chains, as shown in Fig 1. Notice that the output of the analog canceller is added to the received signals before their input to the RX RF chains. We utilize the notation to represent the signal processing realized by the analog canceller. Depending on the deployed hardware components, the analog canceller can have as inputs analog or digital signals. In Sec III, we will detail the hardware characteristics of our two novel analog canceller architectures. We will also show that for both architectures, the baseband representation for the output signal of the analog canceller at node , which we label as , is given by
(2) 
By assuming that the digitally converted and downsampled output signals of the RX RF chains at node are linearly processed in baseband by the combining matrix , the estimated symbol vector for is derived as
(3) 
where the complexvalued element vectors and are the baseband representations of the received signal of interest and received SI signal, respectively, at node . In addition, denotes the received AWGN vector at node with covariance matrix . The vector in (3) is given by
(4) 
where is the uplink channel matrix (ie, between nodes and ), while is obtained as
(5) 
with denoting the SI channel seen at the RX antennas of node due to its own downlink transmission.
For cases where the residual self interference in (3) (ie, after performing analog cancellation and TX/RX digital BF) is above the noise floor, further digital selfinterference mitigation [19] can be applied on the signal to bring the residual interference below that floor. In this paper we focus on analyzing the combined effect of analog cancellation and TX/RX digital BF, hence, we do not model a digital selfinterference cancellation stage.
Iii Novel Analog Canceller Architectures
In this section we present the hardware components of our two novel analog SI canceller architectures. The first architecture is based on the utilization of analog taps and is thus labeled as multitap canceller. The second architecture consists of AUX TXs and termed as multiAUXTX canceller. The joint design of the analog canceller parameters and TX and RX digital BF will be detailed in the following sections.
Iiia MultiTap Analog Canceller Architecture
The hardware components of the proposed multitap canceller for the FD MIMO node are illustrated in Fig. 2. In this figure, canceller taps are applied via MUXs to the outputs of the TX RF chains and via DEMUXs and adders to the inputs of the RX RF chains. One way of implementing analog RF MUXs/DEMUXs is through RF switches. With the term ‘tap’ we denote a fixed delayvariable phase shiftervariable attenuator line, as considered in [14]. It is shown in Fig. 2 that the input of each analog canceller tap is connected to a corresponding to1 MUX which allows routing of any of the TX RF chain signals to the input of the tap. The connection from each TX RF chain to each MUX input can be done via power dividers or directional couplers [14]. The signal that inputs to a tap undergoes a delay, phase shift, and attenuation, and this generates as an output an analog cancellation signal. The output of each tap is connected to a 1to DEMUX, which routes the cancellation signal at the output of the tap to one of the adders located just before the RX RF chains. There is a total of such adders and we use “Adder ” to label the adder that connects DEMUX to RX RF chain . Thus, the signal input to the th RX RF chain is the result of adding cancellation signals to the signal received at the th RX antenna element. Since the adders are connected to DEMUXs, some of the adders may have zero in one of the inputs depending on the DEMUXs’ settings. The adders before the RX RF chains can be implemented via power combiners or directional couplers.
As illustrated in Fig 2, analog SI cancellation is applied to the signals received at the RX antenna elements before these signals enter to the RX RF chains. Recall from Sec II that we utilize the notation to represent the signal processing realized by the analog canceller. Thus, for the multitap canceller architecture in Fig 2, captures the configuration of the MUXs/DEMUXs and the canceller tap values. We model in baseband representation as the following cascade of three matrices
(6) 
where , , and . The elements with and , and with and take the binary values or , and it must hold that
(7a)  
(7b) 
The th row of indicates the MUX configuration at the input of the th tap of the canceller, while the th column of shows the DEMUX configuration at the output of the th tap of the canceller. The in (6) is a diagonal matrix whose complex entries represent the attenuation and phase shift of the canceller taps; particularly, the magnitude and phase of the element with specify the attenuation and phase of the th tap. Recall that the tap delays in each canceller tap are fixed and since we focus on a narrowband system, we model the effects of the th tap delay as a phase shift that is incorporated to the phase of .
The adoption of MUXs/DEMUXs for signal routing is a novel feature of our multitap canceller. The flexible signal routing that is enabled by the MUXs/DEMUXs allows the use of reduced number of taps for analog cancellation, compared to the number of taps required by the designs in [12, 6, 14], which require at least one tap between each TX RF chain and each RX RF chain hence at least taps. For our proposed multitap canceller design, the total number of taps is flexible and can be chosen offline as a function of node size constrains, cost per tap, or other constraints on the analog canceller hardware. Furthermore, the TX and RX digital beamformers and analog canceller will adapt to each others capabilities via our proposed joint design of analog cancellation and digital BF, which will be explained in Sec IV.
IiiB MultiAUXTX Analog Canceller Architecture
Figure 3 depicts the hardware components of the proposed multiAUXTX canceller for the FD MIMO node . The analog cancellation signal is generated through AUX TXs, which are connected via DEMUXs and adders to the RX RF chains. An AUX TX is a TX RF chain that is used locally to generate the cancellation signal; as such, the AUX TX does not require a PA. The input to the AUX TX RF chains is generated in the digital domain and is obtained from a linear transformation of the output signals of the TX digital beamformer. We represent this linear transformation of the transmitted signal to generate locally the cancellation signal by the matrix . It is emphasized that in the multiAUXTX architecture a copy of the SI signal is fed to the analog canceller in the digital domain, whereas in the multitap architecture depicted in Fig. 2 this connection takes place in the analog domain. However, the analog canceller outputs an analog signal for both proposed architectures. The output of each AUX TX feeds a corresponding DEMUX whose role is to route its input signal to one of the adders it is attached to. The latter mechanism is analogous to the DEMUX and adder connections of the multitap canceller described in Sec IIIA. The baseband representation of the signal processing realized by the multiAUXTX canceller is modeled similar to the multitap case by the matrix , which is now given by
(8) 
where . The th column of indicates the configuration of the DEMUX connected to the th AUX TX RF chain. Thus, the elements with and take the binary values or , and it must hold that
(9) 
The flexible routing of the outputs of the AUX TXs via DEMUXs that enables adjustable processing of the SI signal is a novel feature of our multiAUXTX canceller. The designs [15, 13] that adopt AUX TX RF chains do not include DEMUXs and utilize one AUX TX RF chain per RX RF chain (eg, AUX TX RF chains will be needed for node with the designs [15, 13]). This means that if the number of RX RF chains increases, the hardware required for the analog canceller increases as well. In contrast, our proposed multiAUXTX architecture can have any number of AUX TXs, and the effective use of the available AUX TX RF chains will be handled via the joint design of analog cancellation and digital BF, which will be detailed in the following section.
Iv Proposed FD MIMO Optimization Framework
In this section we present a novel FD MIMO optimization framework for the joint design of the hardware components of our analog canceller architectures described in Sec III together with the TX and RX digital BF blocks included in our system model in Fig 1 in order to satisfy certain performance objectives. Capitalizing on the signal model introduced in Sec II, we are particularly interested in the joint design of the analog canceller matrix , the digital precoding matrix , and the digital combining matrix for the FD MIMO node . We define the general objective function having as inputs the latter matrices and representing either a sole scalar performance objective, such as the average sum throughput of the FD MIMO operation, or a multiobjective performance function [20], like the average sum throughput together with energy efficiency. Our general optimization framework for the joint design of , , and at node is mathematically expressed by the following general optimization problem^{1}^{1}1The proposed optimization framework focuses on the joint design of the core processing blocks at the FD MIMO node for a given power budget , without considering the processing at nodes and . A more general problem formulation for the considered system would include in the joint optimization the power allocation between downlink and uplink as well as the RX combining at node and the TX precoding of node . However, in this paper, we study FD MIMO operation at node with conventional downlink and uplink control communication, and we leave the more general joint optimization that would require additional control phases for the communication of the optimized parameters as future work.:
where constraint relates to the total transmit power budget at node and constraint refers to the hardware capabilities of the analog canceller, which impose certain limitations on the construction of . It follows from the discussion in Sec IIIA that for the proposed multitap canceller architecture specifies to
(C2a) 
whereas for the multiAUXTX canceller architecture can be expressed using the description of Sec IIIB as
(C2b) 
In addition, constraint including the general vector function sets the threshold values inside the vector on functions of the instantaneous residual SI appearing at the RX antenna elements after analog cancellation and before the RX RF chains. Two examples of function are: i) the elementwise instantaneous powers of the residual SI signals; and ii) their summation. For the former example, results to with , whereas for the latter example and consequently . Finally, constraint with the general vector function imposes the values included in the vector on functions of the instantaneous residual SI signals obtained after applying analog cancellation and RX digital combining. Similar to , instances of function are the individual instantaneous powers of the latter signals as well as their summation.
The main novel components of the proposed FD MIMO optimization framework in can be summarized as follows. First, the digital TX and RX BF design takes into explicit account the available number of analog taps , or number of AUX TXs , of the analog SI cancellation block. Although some available BF solutions [4, 16, 18] for FD MIMO systems consider the presence of an analog SI canceller, the details of its hardware limitations are excluded from the BF design. Second, the proposed FD MIMO framework is the only one that explicitly considers the case where , ie, the available number of analog taps, or AUX TX RF chains, may be smaller than both the numbers of TX and RX RF chains. This is an important feature for practical FD MIMO deployments, since current analog SI cancellation solutions require either very large numbers of taps, of the order of for the architecture proposed in [6], or very large number of AUX TXs, of the order of for the architecture presented in [15]. Third, our framework has the advantage of a more optimized utilization of the spatial DoF offered by the available multiple antennas at the FD MIMO node . For example, if the analog canceller consists of only tap, or AUX TX, then its cancellation capabilities are very limited, and more spatial DoF need to be devoted from the TX and RX BF blocks for meeting the thresholds and in and . On the other extreme, if can be afforded to be large, the digital BF design may exploit the fact that a significant part of SI mitigation is handled by the analog canceller, and thus, make use of more of the available spatial DoF for improving the quality of the incoming and outgoing signals of interest.
V An Example FD MIMO Design
Capitalizing on the general optimization framework for the joint design of , , and at the FD MIMO node described in Sec IV, we hereinafter present an example joint design of analog cancellation and digital BF. We assume that there is no internode interference between the half duplex multiantenna nodes and due to, for example, appropriate node scheduling [9, 10] for the FD operation of node . Extensions considering this interference for the cases where it is known at either the receiving node and/or the transmitting node or unknown to both are left for future works. The latter assumption translates to setting the channel matrix between the involved nodes as . For this case, the model given by (1) for the received signal at node reduces to
(10) 
We rewrite the signal model (3) that describes the estimation for at the RX of node as
(11) 
where denotes the effective SI channel after performing analog cancellation, which is defined as .
An important performance objective function for the considered system is the FD rate defined as the sum rate of the downlink and uplink communications. We therefore focus on designing , , and via the solution of the following optimization problem:
In the latter problem, the achievable downlink rate is a function of only the digital precoding matrix and is given by
(12) 
Note that we have assumed capacityachieving combining at node in (12), like the nonlinear Minimum Mean Squared Error (MMSE) successive interference canceller [21, Chap 2]. The uplink rate in is a function of , the analog canceller matrix , and the digital combining matrix , and is derived as
(13) 
where denotes the covariance matrix of the interferenceplusnoise after combining at node that can be expressed as
(14) 
Different from downlink rate in (12), in (13) and (14) we include the considered linear combining matrix which jointly with and we aim to optimally design.
Note that in the formulation of we have relaxed constraint concerning the instantaneous residual SI after analog cancellation that appears in the general to an average power per RX RF chain constraint, where the average is taken over all possible transmit symbol vectors. This constraint imposes that, at the input of each of the RX RF chains, the average power of the SI signal for all transmitted symbols within a coherent channel block cannot be larger than the threshold . Notice also that in we have not included a constraint similar to for the residual SI signal after digital combining. Instead we have only incorporated a constraint on the norm of the rows of . The reason for this simplification mainly lies on ’s sum rate objective function. We expect that the joint design of , , and optimizing the uplink rate will naturally result in keeping the average power of the residual SI signal after both analog and digital processing at an acceptable level; acceptable level is any level allowing uplink communication. Furthermore, the unity constraint on the norm of each of the rows of excludes combining solutions that result in undesired amplification of the received signals (ie, the signals from node , SI, and AWGN).
We propose to tackle with the following twostep approach. First, as described next in Sec VA, we consider only the downlink which is usually more rate demanding than the uplink, and obtain the pairs of and designs optimizing the instantaneous downlink rate while meeting their respective constraints. Then, we solve for the best pair of and as well as the design that jointly maximize the sum rate performance, as will be explained in Sec VB.
Va Candidate Designs for and
We first formulate the following downlink rate maximization problem using (12) for the design of and at node :
To solve the latter problem we adopt an alternating optimization approach. Specifically, supposing that a realization of the analog canceller satisfying is given, we seek for the TX digital precoder maximizing the downlink rate, while meeting and the threshold . Note that each realization of the analog canceller corresponds to a distinct MUX/DEMUX configuration. Let us assume that for taps (or AUX TXs, depending on the underlying canceller architecture) there are in total distinct realizations for the analog canceller, where with denotes the th canceller realization. Recall that , the number of taps or AUX TXs, is decided offline upon hardware design as a function of size constraints, cost per tap and cost per AUX TX RF chain, or other hardware constraints. Examples of realizations for the analog canceller are given at the end of this section. We use the notation to represent the precoder design solving for each specific . The alternating optimization approach is repeated for in order to find the best pair of canceller and precoder solving . The solution for given is summarized in Algorithm 1. The precoder is iteratively constructed as the cascade with and , where is a positive integer taking the values and holds that . In general, , however, for large transmission powers and strictly small values for it is advisable to set . For each value of we adopt a similar approach to [7] for the precoding design. Particularly, its component aims at minimizing the impact of the residual SI MIMO channel , whereas the goal of the component is to maximize the rate of the effective downlink channel . Intuitively, parameter represents the effective number of TX antennas after squeezing SI in the least dominant modes of via the efficient use of . For the cases where is a MIMO channel, the precoder in Step 5 of Algorithm 1 is given by the openloop or closedloop precoding for this channel derived using [22], depending on whether is unknown or known, respectively, at the transmit side of node . In the simulation results shown later on in Sec VI we will use openloop precoding. When and , is a Multiple Input Single Output (MISO) channel, and if its knowledge is available at node , the optimum precoding is Maximal Ratio Transmission (MRT). If is a Single Input Multiple Output (SIMO) (ie, for and ) or a scalar (ie, for ) channel, is a scalar set to .
As seen from Step of Algorithm 1, the solving for a specific is given by . This notation represents the precoder corresponding to the largest value of that results in meeting constraint ; recall that determines and dimensions. We denote the maximum value of for the design as , and also use the notation with for the th candidate precoder solution for given . Although, the included iterations for solving this problem could be terminated when is found, Algorithm 1 computes meeting ’s threshold and optimizing the downlink rate for a given . Among those designs, the ones corresponding to lower values of (ie, those with increasing index ) naturally result in larger SI mitigation. Although this behavior is desirable for maximizing the uplink rate, ’s with larger (ie, obtained from lower ) yield lower downlink rates. On the contrary, maximizing the downlink rate creates the stronger SI signal contaminating the uplink. Hence, our goal with Algorithm 1 is to capture this trade off and obtain solving for a given . Running this algorithm for all possible canceller realizations finally results in the joint canceller and precoder designs and and , which are feasible candidate solutions for . Those pairs will be used in Sec VB for obtaining the joint analog canceller and the TX/RX digital BF solution of .
Algorithm 1 is executed at the FD MIMO node and has as inputs the MIMO channels and as well as a realization . Both and can be estimated through appropriately designed training processes at nodes and , respectively. The latter matrix estimation can be fed back or not to node depending on whether openloop or closedloop MIMO operation, respectively, is adopted. We next discuss meaningful realizations for both the proposed analog SI canceller architectures that provide insights on the effects of choice. Note that one can also consider reducing the search of canceller realizations in to a realization that is a deterministic function of or to a desired subset of possible realizations.
Realizations for the MultiTap Canceller. For a given number of taps there are in total ways to connect the taps from the available TX antennas to the available RX antennas. This results in at most possible realizations for the multitap canceller. Each of those refers to a different matrix and corresponds to a specific placement of the tap values inside ; its remaining elements (ie, ) need to be set to zeros. One reasonable intended for satisfying the SI constraint in is to obtain , , and such that the resulting analog canceller matrix has the tap values at the same elements with the largest in amplitude elements of . This will result in cancelling the largest SI signal components. For example, suppose that , , and and that and are the two largest in amplitude elements of . In this case, we may design , , and . Other reasonable ’s include the orderly columnbycolumn and rowbyrow placement of the available tap values starting with the columns and rows, respectively, of having the largest Euclidean norms. For example, suppose that , , , and that the second RX antenna is the one most affected by SI (ie, the one affected by the largest SI energy). Then, having the three tap values placed at the second row of will focus on reducing the SI received at the second RX antenna element. Generally, having tap values placed at the th row results in reducing SI at the th RX antenna. In the simulation results with this architecture we opt for the latter canceller design, namely the rowbyrow placement of the tap values, starting with ’s row having the largest Euclidean norm and continuing with the rest rows in descending ordering of Euclidean norms, if there are more taps to be assigned.
Realizations for the MultiAUXTX Canceller. To satisfy the constraint of AUX TXs, each canceller matrix needs to have allzero rows. The nonzero rows specify the connection of the DEMUXs and the linear operation applied by . There are in total ways to connect the output of the AUX TXs to the RX antennas, and each way corresponds to a specific placement of the nonzero rows inside the canceller matrix. This results in at most possible realizations for the multiAUXTX canceller. One reasonable realization, which we use in our simulation results for this architecture, corresponds to the case where the AUX TX RF chains are connected to the antennas that are receiving the largest SI energy. This realization targets ’s rows having the largest Euclidean norms. Connecting the th AUX TX RF chain to the th RX antenna corresponds to setting .
VB Joint Design of , , and
Using the candidate designs and and for solving from the approach in Sec VA, we now proceed to the final joint design of the analog canceller and TX/RX digital BF at node maximizing the instantaneous FD rate. In particular, we formulate the following optimization problem using (12) and (13) for the computation of the best pair of and together with the optimum :
To solve we adopt the following exhaustive search approach. For each of the pairs of analog canceller and TX digital precoder obtained in the previous step as candidate designs for solving , we compute maximizing the uplink rate given by (13), while meeting its respective constraint included in both and . Then, for each computed and its corresponding and pair we calculate the achievable FD rate. The joint design maximizing the FD rate provides the solution for . To solve the uplink rate maximization problem we assume that and appearing in (13) and (14) are available at node through appropriately designed training phases. With the availability of this channel knowledge and a pair of and , it can be shown that the maximizing the UL rate is given using [23, Sec 4.2] by , where has as columns the left singular vectors of corresponding to its respective nonzero singular values. The diagonal matrix and the matrix are obtained from the eigenvalue decomposition of the interferenceplusnoise covariance matrix at node , which is defined as
(15) 
The eigenvalues of are included in the main diagonal of , while the columns of include their corresponding eigenvectors. The diagonal matrix ensures the constraint is met. The th entry of is equal to . For the special case of [1], which consequently results in , the solution combining vector simplifies to the eigenvector corresponding to the maximum eigenvalue of the matrix given by [24]
(16) 
where we have used the notation . We note that for the practical case of imperfect analog cancellation, significant gains with the considered RX digital combining are feasible only when it holds .
VC Remarks
We next provide some subtleties of our example FD MIMO design and possible extensions. We note however that, even without the following extensions, our presented design outperforms the SotA solutions, as will be shown in Sec VI including our performance evaluation results.
Remark 1: The presented solutions of for the analog cancellation and TX/RX digital BF are functions of the MIMO channel matrices , , and . This implies that the update of the BF settings as well as the settings of the canceller (values for the taps or AUX TX RF chains as well as MUX/DEMUX configurations) depend on the coherence time of the involved wireless channels.
Remark 2: Solving is feasible when there exists at least one pair of and meeting the constraint. When such a pair does not exist, uplink communication is impossible to take place simultaneously with the downlink one (ie, FD communication for the given and is infeasible). We note that for our FD rate results appearing in Section VID we only focus on scenarios where solving is feasible. For cases where a and pair satisfying does not exist, can be solved via half duplex communication, and there is no need for a canceller design. In this case, the solution is either the precoder maximizing the downlink rate or the combiner maximizing the uplink one, depending on which of the two results in the maximum half duplex rate. If we relax the SI constraint in and to a subset, instead of all, RX RF chains (ie, suppose that the constraint becomes with ), FD communication is more probable to be feasible for a given and . This happens because with this relaxation we allow uplink communication even when there exist at most RX RF chains experiencing average residual SI power larger than . However, those saturated RX RF chains should not be considered for reliable reception, hence, they should be deactivated for uplink communication via adequate antenna selection. Under this strategy, the uplink MIMO matrix is denoted by being a submatrix of , where the rows corresponding to the saturated RX RF chains have been excluded. It is finally noted that both the value for , and to which specific RX RF chains the constraint is imposed, will impact the achievable uplink rate, and hence the feasible FD communication.
Vi Simulation Results and Discussion
The performance of the wireless communication scenario illustrated in Fig. 1 using the FD MIMO design presented in Sec V is evaluated. In Sec VIA we describe the SotA solutions with which the proposed solutions will be compared. The simulation parameters and assumptions are then detailed in Sec VIB, whereas the SI mitigation capability and achievable rate results for different hardware complexity levels are presented in Secs VIC and VID.
Via Compared FD MIMO Designs
We compare our novel FD MIMO design versus the combined cancellation and spatial suppression design presented in [4] as well as the digital BF design proposed in [7]. We note that the designs presented in [16, 17] were not considered in the results that follow due to the fact that they are only applicable to UpLink (UL) and DownLink (DL) communication with , whereas our proposed solutions hold for . A detailed description of the FD MIMO designs that will be compared is provided below.
Design 1: Proposed with taps. This is our proposed FD MIMO design with a tap analog canceller. Compared with the SotA architectures [6, 14] requiring at least taps, our canceller results in % reduction in the required taps’ numbers. The TX/RX digital BF as well as the settings for the canceller at the FD MIMO node are computed as presented in Sec V. For being a MIMO channel, we have adopted openloop MIMO precoding for the computation of .
Design 2: Proposed with AUXTX. This is our proposed FD MIMO design for the case of multiAUXTX canceller with AUX TX RF chains. Compared with the SotA architectures [13, 15] which require at least AUX TXs, our canceller results in % reduction in the required number of AUX TXs. We have again used Sec V for the computation of TX/RX digital BF as well as the canceller settings at the FD MIMO node . The computation was the same as for Design 1.
Design 3: SotA with taps. This refers to a combination of time domain analog cancellation with spatial suppression as proposed in [4]. The TX beamformer is designed to minimize SI caused from this operation by using null space projection [4] for this communication side. The RX BF was proposed to be a MMSE filter in [4], we however utilize the optimum combiner obtained using [23, Sec 4.2], as explained in Sec V. Hence we use the same combiner as in Designs 1 and 2. The time domain cancellation is a canceller that requires in total taps (ie, one tap per TXRX RF chain), as in the SotA schemes [6, 14]. We have made the same assumptions for the hardware capabilities of the taps for this design as in Design 1.
Design 4: SotA with AUXTX. This design is similar to Design 3 but uses AUX TXs in place of the analog taps. It particularly combines time domain cancellation with spatial suppression [4]. The former is an analog canceller requiring a total of AUX TX RF chains (ie, one AUX TX RF chain per RX RF chain), as in the SotA schemes [13, 15]. In addition, the hardware capabilities of each AUX TX are considered the same with our Design 2. TX digital BF is designed for SI minimization from the TX side, whereas RX digital BF is given by , as described in Sec V.
Design 5: SotA with taps/ AUXTX. This is the SoftNull method presented in [7] that does not adopt analog cancellation, relying solely on TX digital BF to reduce SI at the RX antennas of node . Any residual SI is handled by the RX digital combiner. The combiner used in the previous designs is used for the latter purpose.
ViB Simulation Parameters
We have assumed Rayleigh fading and a path loss of dB for both the DL and UL channels. The SI channel is assumed to be subject to Ricean fading with factor equal to dB and path loss of dB [25]. All involved wireless channels are assumed to be Independent and Identically Distributed (IID), and perfectly estimated at the receivers (ie, at the RXs of nodes and ). We have used independent channel realizations for all statistical results. The DL transmit power was set between dBm and dBm, and the UL transmit power was set 20dB lower, hence spanning a range from dBm to dBm [26]. The noise floor at node is dBm and at node is dBm. The latter values are typical ones for small cell base stations and mobile terminals. Following the findings of [2] we consider a bit ADC at node that renders digital SI mitigation of approximately dB feasible. This means that for the noise floor of dBm at node the residual SI after analog cancellation (ie, at each RX RF chain’s input) must be less than dBm. In Appendix A we detail the two realistic models used for simulating nonideal analog canceller hardware. The one model concerns the proposed multitap canceller architecture and the other the multiAUXTX one. According to these models, the multitap canceller is capable of delivering approximately dB of analog cancellation per tap, whereas the multiAUXTX canceller offers approximately dB of cancellation per AUX TX RF chain.
ViC SelfInterference Mitigation Capability
We consider a FD MIMO node (ie, ) and two different cases for the number of antennas at nodes and : the singleantenna case (ie, ) and the multiantenna with . We investigate in Figs 4–7 the probability that the residual SI after analog cancellation meets the constraint of being less than dBm. Results are shown for both proposed multitap and multiAUX TX architectures for various hardware complexity levels, as implicated by different values of for the taps and AUX TXs, respectively. Within Figs 4–7 we also sketch results for SotA designs with taps and with AUX TXs, as well as for the only digital SotA solution (ie, taps or AUX TXs). For the latter design, we have one DL stream for the precoder, since this was the configuration yielding the largest SI reduction, however, as shown from all Figs 4–7, for dBm, this design is incapable of guaranteeing residual SI power levels at any of the RX RF chains below the required dBm. Figures 4 and 5 demonstrate that the proposed multitap based design ensures that the residual SI power satisfies the constraint for all considered TX powers for and taps, which translates to % and % less taps compared to the SotA requiring taps. In addition, Figs 6 and 7 showcase that the proposed multiAUX TX solution with and AUX TXs is the only one based on AUX TXs that is capable of offering residual SI power below dBm for all values. Actually, the SotA design with AUX TXs (ie, with % and % more AUX TXs than the and AUX TXs cases) cannot meet the residual constraint for dBm.
We now investigate in more detail how our proposed joint analog cancellation and BF design adapts in order to meet the constraint on residual SI, while providing spatial resources for DL and UL communications. Recall that used in the precoder solving determines the effective number of TX antennas used for DL data transmission. An close to means that the TX BF of the FD node is using more antenna resources for improving DL than for SI reduction. Therefore, determines the tradeoff between acceptable SI levels as well as DL and UL achievable rates. In Figs 8 and 9 we illustrate the average values of chosen by our FD MIMO design as function of the DL and UL TX powers for the case of the multitap architecture (for and taps) and multiAUX TX architecture (for and AUX TXs) respectively and for and . From these figures we observe that for a given and , the value of increases as the number of taps (or AUX TXs) increases. For example, in Fig 8 for , the values of for taps are always larger that the values of for taps. The more taps (or AUX TXs) the more analog canceller resources for SI mitigation, and hence less antenna resources are required for this mitigation in order to meet the residual SI constraint. This is why our algorithm chooses a larger as the number of taps (or AUX TXs) increases. Thus, the results in Figs 8 and 9 verify that our FD MIMO design is capable of judiciously dividing the burden of SI mitigation between the analog canceller and the TX digital BF by taking into account the resources available for analog cancellation.
Another observation from the results in Figs 8 and 9 is that as the number of RX antennas in DL and/or the number of TX antennas in UL increase, our FD MIMO design tends to be more conservative in the choice of since it chooses a smaller value for . For example, in Fig 8 for the case of taps, the values of for are larger than those for The reason for this behavior is as follows. Recall that the number of UL streams is equal to . Since then as increases from to there will be more streams in the UL communication. This increment of UL streams makes the design of TX digital BF more demanding since it has to steer SI away from these several incoming UL streams in order to maximize FD rate. Thus, our FD MIMO design chooses the small so that the FD node can put more effort on SI mitigation. Serving less streams in DL by choosing a lower