LHCb VELO Upgrade

The Large Hadron Collider Beauty detector lhcb () (figure 1) is a flavour physics detector, designed to detect decays of $b$- and $c$-hadrons for the study of CP violation and rare decays. In pp collisions at LHC lhc () energies, $b\overline{b}$ production is primarily in the forward/backward direction. LHCb has been designed as a forward arm spectrometer, to exploit this fact. LHCb is a precision experiment operating at a instantaneous luminosity of $L$ = 4$\times$10 ${}^{32}$${cm}^{-2}{s}^{-1}$, and is expected to continue in its current configuration until 2018.

At the end of Run-II, many of the LHCb measurements will remain statistically dominated. Luminosity will be increased by a factor of five to $2\times {10}^{33}$${cm}^{-2}{s}^{-1}$in Run-III. The increased luminosity at LHCb will boosts statistics primarily in semi-leptonic channels containing at least one muon. However, the trigger yield for purely hadronic decay channels saturates due to energy cuts in the hardware trigger. Removing the hardware trigger eliminates the 1 MHz bottleneck and improves the efficiency due to having full information available for the first level trigger decision Running the detector at 40 MHz requires radical changes to many of the subdetectors of LHCb.

The VELO velo ()kazu () is a silicon strip detector surrounding the interaction point at LHCb. The sensors are made of 300 $\text{upmu}m$ $n^{+}\text{-}on\text{-}n$ silicon, and are positioned only 7 mm from the beam line during data taking. The VELO is split into two halves such that each can be retracted during LHC injection. The two VELO halves are operated in vacuum and separated from the primary LHC vacuum by means of a 300 $\text{upmu}m$ thick aluminium foil. The VELO is required to have excellent impact parameter resolution, essential for the reconstruction of heavy hadron decays.

The VELO consists of 42 modules placed along the beam direction, with the full length of the detector being approximately 1m. A module is made of two half-disc sensors with R- and $\Phi$-measuring geometry.

The Vertex Locator upgrade veloup () is a significant redesign from the original detector. The major changes in new detector and its predecessor are as follows:

• The detector will change from a silicon strip detector to a pixel detector.

• The detector will be closer to the beam in its closed position at 5.1 mm from 8.2 mm

• The upgraded VELO will use a new VeloPix ASIC velopix () that can be read out at 40 MHz (up from 1.1 MHz) and a bandwidth of up to 20.4 Gb/s.

• The current detector modules are cooled with ${CO}_2$ passing through a series of cooling blocks attached to the base of the module substrate. The upgraded modules will also use ${CO}_2$ as a coolant, but it will pass through micro-channels in a silicon substrate, directly beneath the major heat sources (VeloPix ASICs and other chips).

The upgraded VELO (shown in figure 2) will have more robust track reconstruction performance compared to a strip detector and an overall improved resolution (figure 3). This improved performance is achieved by (i) lowering the material budget with thinner sensors and and thinner aluminium foil housing each detector half and (ii) placing the sensors closer to the beam. The closer placement of the detector modules to the beam and the higher luminosity for LHC Run III comes with some costs - the detector must be able to handle higher radiation doses; there is a higher hit occupancy due to increased particle flux. This, in turn, results in higher data rates from the detector and greater power consumption in the front-end ASICs (however, the dominant increase in data rate is due to the removal of the L0 hardware trigger). Table 1 lists some of the major differences between the current VELO detector and the upgrade.

A campaign of beam tests were performed throughout 2014 and 2015 to characterise the performance of candidate VELO upgrade sensors. The two major vendors studied were Hamamatsu (HPK) and Micron. Testing was performed with a Timepix3 telescope. Timepix3 is a precursor of the VeloPix ASIC but runs at a lower data rate (80 Mhit/s, compared to 900 Mhits/s for VeloPix). VeloPix has binary readout, whereas Timepix3 has analogue readout yielding a better time and spatial resolution. Timepix3 has the same pixel geometry as VeloPix and therefore was an ideal test-bed for characterising the VELO upgrade sensors²²2The VeloPix design had not been finalised at the time of sensor testing.

The upgrade sensors will receive an highly non-uniform radiation dose up to $8\times {10}^{15}MeV\cdot n_{eq}/c{m}^{-2}$ during their lifetime. At this dose, the sensors are expected to retain a 99% hit efficiency at up to 1000 V bias voltage without suffering breakdown. The HPK and Micron sensors tested with the Timepix3 telescope were compared un-irradiated and irradiated to their maximum dose ($8\times {10}^{15}MeV\cdot n_{eq}/c{m}^{-2}$ equivalent to an integrated luminosity of 50${\text{,fb}}^{-1}$). The single hit resolution of detectors is shown in figure 6 and the charge collection performance is shown in figure 7. Sensor tests defined a baseline choice of 200$\text{upmu}m$ n-on-p silicon as suitable for the VELO upgrade. This is subject to change if, for example, a similarly performing thinner sensor be found.

At the heart of new VELO upgrade electronic design is the new VeloPix ASIC velopix (). The VeloPix is based on the Timepix3 ASIC and has a data-driven readout. The $256\times 256$ pixel array is arranged into groups of $2\times 4$ pixels called SuperPixels. Binary hit information is time-stamped, addressed and read out as SuperPixels packets. Arranging the data in this way reduces the output bandwidth by $\approx 30\%$ over standard pixel readout. The data readout latency varies as a function of SuperPixel hit position, and hits closer to the beam take longer to reach the end-of-column readout logic. In addition, the hits will be disordered in time.

The VeloPix will be read out using a PCIe40 readout board pcie40 () which has been designed as a generic readout board for the LHCb upgrade. The PCIe40 firmware is designed as a series of common components with the option for user-specific data processing. The common components deal with accepting the input data from the detector over the GBT protocol gbt (), error-checking, dealing with reset signals, and preparing the data for the event builder and computing farm. The user-specific code would, for example, perform zero-suppression or similar data-reduction techniques.

For the VELO upgrade, some of the common input blocks have had to be replaced as the GBT protocol is not used for reasons of power consumption at the front-end. A simpler protocol - Gigabit Wireline Transmitter (GWT) has been used instead. The VELO user-specific blocks include primarily (i) data descrambling, decoding and parity checking, (ii) a time-ordering router which re-sequences the data coming from the continuous readout of the VeloPix chip, and (iii) a hit isolation tagger which performs a simplified type of clusterisation to reduce the load downstream in the reconstruction software running on the CPU farm. Resource utilisation within the FPGA is within acceptable tolerances and studies of packet loss rates are ongoing. Preparations are being made to assess VeloPix readiness.

The VELO upgrade detector makes significant improvements on its predecessor. Improved tracking performance is achieved using a pixel sensor closer to the interaction region (5.1 mm) but with a reduced material budget. This leads to an even higher and non-uniform radiation tolerance requirement. As such the sensors and readout chips are cooled using a ${CO}_2$ coolant via a microchannel silicon substrate. Candidate sensors meeting the required performance constraints have been identified. Significant progress has been made to both control and read out the forthcoming VeloPix chip which will be tested in the coming months.

Thanks to Science Technology Funding Council (STFC) of the UK, University of Liverpool, CERN and associated institutes of LHCb.