[

[

Hema C.P. Movva hemacp@utexas.edu    Amritesh Rai    Sangwoo Kang    Kyounghwan Kim    Babak Fallahazad Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78758, USA    Takashi Taniguchi    Kenji Watanabe National Institute of Materials Science, 1-1 Namiki, Tsukuba, 305-044, Japan    Emanuel Tutuc    Sanjay K. Banerjee Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78758, USA
Abstract

We demonstrate dual-gated p-type field-effect transistors (FETs) based on few-layer tungsten diselenide (WSe) using high work-function platinum source/drain contacts, and a hexagonal boron nitride top-gate dielectric. A device topology with contacts underneath the WSe results in p-FETs with / ratios exceeding 10, and contacts that remain Ohmic down to cryogenic temperatures. The output characteristics show current saturation and gate tunable negative differential resistance. The devices show intrinsic hole mobilities around 140 cm/Vs at room temperature, and approaching 4,000 cm/Vs at 2 K. Temperature-dependent transport measurements show a metal-insulator transition, with an insulating phase at low densities, and a metallic phase at high densities. The mobility shows a strong temperature dependence consistent with phonon scattering, and saturates at low temperatures, possibly limited by Coulomb scattering, or defects.

Transition metal dichalcogenide (TMD), tungsten diselenide (WSe), field-effect transistor (FET), metal-insulator transition (MIT), hole mobility

WSe2 FETs]High-Mobility Holes in Dual-Gated WSe Field-Effect Transistors

The isolation of graphene, and study of its exceptional properties has triggered an interest in several other two-dimensional (2D) layered materials1, semiconducting transition metal dichalcogenides (TMDs)2, 3 being one of them. In contrast to graphene’s zero band-gap, semiconducting TMDs have a large (1-2 eV) band-gap, making them potentially useful for future electronic devices requiring high / ratios. The diverse variety of semiconducting TMDs such as molybdenum disulfide (MoS)4, 5, molybdenum diselenide (MoSe)6, tungsten disulfide (WS)7, tungsten diselenide (WSe)8, 9, 10, 11, each having its own thickness dependent electronic band-structure, provide a wide choice for specific use in optoelectronics, low-power, and/or high-performance device applications12, 9, 5. In addition, the coupled spin and valley degrees of freedom, and massive charge carriers in TMDs result in a wealth of novel electrical, and optoelectronic phenomena13, 14 that can be exploited for the development of alternative device architectures15, 16. To date, MoS has received the most attention among all TMD field-effect transistors (FETs), with the devices exhibiting n-type conduction4, 5, 17, 18, 19, 20. It is equally important to explore p-type TMDs, in order to realize a practical TMD-based post-silicon CMOS architecture. One TMD that has attracted significant attention for p-FETs is WSe, with early reports of bulk-WSe FETs showing hole mobilities approaching 500 cm/Vs11. Subsequently, few-layered WSe FETs have also been demonstrated with high / ratios, and hole mobilities8, 10, 21, 22, 23. While MoTe24, and 2D black phosphorus25 have also been reported to show p-type conduction, these materials are less stable in ambient conditions. The high thermal, and environmental stability, and well-developed materials science of WSe make it very attractive as a channel material for 2D p-FETs11.

Creating low resistance, Ohmic contacts has been a major challenge limiting study of the intrinsic properties of TMDs. Most metal contacts to TMDs form Schottky barriers, resulting in large series resistances which degrade even further at low temperatures5, 9, 10. Considerable research effort has been put into addressing this problem, using techniques such as metal work-function tuning5, 9, 26, contact annealing18, 17, graphene contacts27, 28, 21, electrical double layer (EDL) structures23, 28, 21, and doped source/drain contacts8. While improving the contacts, these techniques however have several limitations like (i) processing constraints, and instability of low work-function metals5, 9, (ii) unintentional doping during contact annealing18, (iii) slow response speed of EDL structures, preventing their use in FETs23, and (iv) instability of surface charge transfer dopants in air8. Whereas graphene contacts result in efficient electron injection in MoS27, the large band offsets between the Dirac point of graphene, and the conduction, and valence bands of WSe29 necessitate additional doping of the graphene for efficient carrier injection21, 28. Moreover, these approaches are primarily directed towards back-gated FET geometries, which are of limited use in practical circuits. There is a need to develop top-gated FET structures in order to enable independent control of multiple FETs on the same substrate towards large scale device integration. Furthermore, an air-stable, low temperature compatible contact scheme is imperative for a systematic investigation of the nature of charge transport in WSe.

In this work, we use high work-function platinum (Pt) as the contact metal for efficient hole injection into the valence band of WSe. By using a device topology with the Pt contacts underneath the WSe, and a pristine hexagonal boron nitride (hBN) top-gate dielectric, we realize dual-gated FETs with contacts that are Ohmic down to cryogenic temperatures. We demonstrate that this contact scheme is optimized for top-gated FET operation, with the back-gate serving as an additional knob to fine-tune the FET characteristics. Top-gated transfer characteristics show / ratios exceeding 10, and hole mobilities around 140 cm/Vs at room temperature in three/four-layer WSe. The output characteristics exhibit current saturation, and a negative differential resistance. Temperature-dependent transport measurements reveal a metal-insulator transition, indicating high device quality. The mobility shows a strong temperature dependence at high temperatures, indicative of phonon dominated transport in this regime. At low temperatures, the mobility saturates, approaching up to 4,000 cm/Vs, possibly limited by Coulomb scattering, or defects21, 18.

1 Results and discussion

We use exfoliated WSe flakes derived from commercially available crystals as the source material for fabricating the FETs in this work. Three/four-layer WSe, and 15-20 nm hBN flakes are identified using optical contrast, Raman spectroscopy, and photoluminescence measurements (S1 in Supporting Information). A polymer-coated silicone stamp30 is used to assemble, and transfer a stack of hBN/WSe on to pre-patterned Cr/Pt electrodes on a SiO/Si substrate. Subsequently, a local palladium (Pd) top-gate is patterned, resulting in a device structure as shown in Figure 1(a). Optical micrographs during the fabrication process are shown in Figure 1(b), and described in detail in the Materials and Methods section.

We chose Pt due to its high work-function ( 6.0 eV)31, which places its Fermi level below the valence band edge of WSe ( + 5.5 eV)29.This band alignment is intuitively expected to result in Ohmic p-type contacts. Choice of appropriate work-function metals has been successfully employed in the past to optimize carrier injection in TMD FETs. Low work-function scandium contacts were found to result in efficient electron injection in MoS5, and indium was used for low-resistance n-type contacts to WSe9. However, Fermi level pinning at the metal-TMD interface has also been found to strongly impact the contacts, resulting in non-trivial behavior for some metal-TMD combinations.5, 9 Furthermore, the metal-TMD interface is highly sensitive to the processing environment such as, vacuum conditions in the deposition chamber, deposition rate, metal topography, etc. These variations can potentially affect the TMD electronic structure, metal crystallinity, and in turn, the metal work-function32, resulting in wide variations in FET characteristics among reports in literature5, 9, 22. By choosing an inert contact metal like Pt, and by decoupling the metal deposition step from creating the actual metal-TMD contact, we can potentially eliminate some of these uncertainties. Direct deposition of Pt on WSe as a top-contact is impractical due to its poor adhesion, whereas, using an adhesion layer such as chromium reduces the effective metal work-function at the contact interface. Our strategy of back-contacts circumvents this problem, since the Pt electrodes can now be deposited with an appropriate adhesion layer at the bottom without affecting the top surface work-function. The transferred WSe would contact the Pt top-layer, whose high work-function would still be preserved. Finally, the choice of hBN as the top-gate dielectric is motivated by its ultra-flat surface, which has been shown to reduce extrinsic impurity scattering in TMDs21, 27, 28.

Figure 1: (a) Schematic of a dual-gated WSe FET with Pt contacts underneath the WSe, an hBN top-gate dielectric, and a Pd top-gate. The biasing scheme is shown in red. (b) Optical micrographs during the fabrication process show (1) a three/four-layer exfoliated WSe flake on SiO/Si, and (2) pre-patterned Pt contacts on a separate SiO/Si substrate. (3) An hBN flake is used to pick-up the WSe, and is transferred onto the Pt contacts, followed by (4) patterning of a local Pd top-gate. The scale bars are 10 m (c) Transfer characteristics of the FET ( = 6 m) at different , showing p-type conduction at as low as 1 mV, and an / ratio at = 1 V. Low-bias output characteristics of the FET at different for the (d) p-branch, and (e) n-branch show Ohmic, and Schottky contacts, respectively. The back-gate is grounded for all measurements.

We evaluate the effectiveness of our back-contact scheme by performing gate-dependent transport measurements. Figure 1(c) shows the top-gated transfer characteristics of a WSe FET with an 18 nm hBN top-gate dielectric at different values of drain bias (), with the back-gate grounded. The biasing scheme is shown in Figure 1(a). The top-gate bias () is applied to the Pd top-gate, the back-gate bias () to the highly-doped Si substrate, and the source terminal () is grounded. Even at a low = 1 mV, the drain current () is found to increase with increasing negative , and an insulating behavior is observed for positive . This indicates predominant hole transport in the WSe for negative , hereafter referred to as the “p-branch”. For larger , however, we observe an increase of even with increasing positive (hereafter called the “n-branch”), symptomatic of emergent electron conduction in this regime. However, while increases proportionally with for the p-branch, the behavior is highly non-linear for the n-branch. The overall behavior hints at Ohmic, and Schottky nature of the Pt back-contacts to the valence, and conduction bands of WSe, respectively. Similar ambipolar characteristics reported for WSe FETs with conventional top-contacts21, 10, 28, 23 confirm that the transferred WSe does indeed form a good electrical contact with the Pt electrodes. Evidence of clear subthreshold, and insulating regimes, along with a high / ratio over 10 (at = 1 V) further demonstrate that the integrity of the WSe is maintained during, and after transfer. The intrinsic nature of WSe is evident from its insulating state around = 0 V, indicating no unintentional doping from the fabrication process. Negligible hysteresis in the transfer characteristics signifies minimal charge trapping, and therefore, clean interfaces in the device. A threshold voltage () of -2 V can be extracted for the p-branch from the linear region of the transfer characteristics. The quality of the hBN dielectric is manifested in the top-gate leakage current, which remains close to the noise floor throughout the measured range (S2 in Supporting Information).

The nature of contacts can be further verified from the low-bias output characteristics that are shown in Figures 1(d), and (e). The characteristics for the p-branch (Figure 1(d)) show a symmetric, linear dependence of on for all negative values of , denoting Ohmic contacts. On the other hand, the trend for positive (Figure 1(e)) is highly non-linear, and asymmetric, indicative of Schottky contacts to the n-branch. It should be noted that the currents for the p-branch are more than three orders of magnitude larger than the n-branch, confirming that Pt is better suited to contact the valence band of WSe. The high work-function of Pt results in a large Schottky barrier to the conduction band which explains the Schottky nature of contacts to the n-branch. Lower work-function metals such as indium, silver,9 nickel10, etc. would be preferable for contacting the n-branch of WSe. The integration of back-side source/drain contacts with a top-gated geometry ensures unimpeded electrostatic modulation of the contact, and channel access regions by the top-gate. By contrast, in top-gated TMD FETs with top contacts, screening by the source/drain electrodes obstructs modulation of these access regions by the top-gate, and the ensuing large series resistances severely limit current injection into the channel, and degrade the FET performance4, 8. Additionally, our device structure with inert metal electrodes, and dielectrics is robust, and can be extended to other TMDs, and TMD heterostructures, where large series resistances are particularly problematic33.

In the following, we focus the discussion on hole transport in our devices. We use multi-terminal four-point measurements to extract the intrinsic hole mobilities, and contact resistances. Figure 2(a) shows the 2-point conductance (), and 4-point, intrinsic conductance () as a function of . While is measured as the conductance between an adjacent pair of contacts, is measured using the voltage drop between the same two contacts when biasing an outer set of contacts (S3 in Supporting Information). The field-effect mobility () is then calculated using

(1)
Figure 2: (a) Transfer characteristics of a WSe FET ( = 6 m, = 12 m) showing variation of (dashed lines), and (solid lines) as a function of , in linear (left, blue) and log (right, red) scales. The black lines show linear fits to Equation 1, resulting in = 48 cm/Vs, and an intrinsic, = 140 cm/Vs. (b) A plot of the variation of vs. shows reducing with becoming more negative due to modulation of the channel access, and contact regions by the top-gate. The back-gate is grounded in (a) and (b). (c) Back-gated transfer characteristics show saturation of in the ON state, which increases as becomes more negative.

where, is the channel conductance, is the top-gate capacitance, and , and , are the width, and length of the channel, respectively. For extracting the 2-point field-effect mobility (), we use = , and for the 4-point, intrinsic field-effect mobility (), we use = . While has contributions from both the intrinsic channel conductance, and contact resistance, is a measure of only the intrinsic channel conductance. The specific contact resistance () can therefore be determined using

(2)

where, is normalized to the contact width, and has units of km. For an hBN thickness of 18 nm (dielectric constant of 3.0), which corresponds to a geometric top-gate capacitance ()21, 18 of 150 nF/cm, = 6 m, and = 12 m, we extract = 48 cm/Vs, and = 140 cm/Vs. The considerably lower value of compared to is due to the detrimental effect of on . Acting as a parasitic series resistance, reduces the effective drive voltage on the channel, thereby reducing , and in turn, . The extracted of 140 cm/Vs compares well with prior reports of intrinsic mobilities in few-layer MoS18, 27, 17, and WSe21, 28, 23. The hole-density at = -5 V can be extracted using

(3)

where, is the charge of an electron, to be = 2.810 /cm. While this value is lower than the carrier densities attainable by EDL structures28, 23, it is comparable to densities in conventional dielectric based FETs22, 21.

The variation of vs. is plotted in Figure 2(b). It can be seen that reduces as becomes more negative, asymptotically approaching 100 k at = -5 V. While exhibiting a larger than values for EDL gated WSe ( 10 k)23, 21, our Pt contacts display superior low-temperature Ohmic behavior. The strong dependence of on is consistent with previous reports of gate-tunable contact barriers at the metal-TMD interface18, 21, 27. Variation of with gate-bias is not observed in traditional MOSFETs due to their highly-doped source/drain regions34. However, if they are undoped, as in typical TMD FETs, the gate can electrostatically modulate the contact regions, and in turn, . Whereas the top-gate can efficiently modulate the contact regions in our structure, screening by the source/drain electrodes prevents modulation by the back-gate. Back-gated FET transfer characteristics are therefore severely series resistance limited, as illustrated in Figure 2(c). While the overall variation of vs. is consistent with hole conduction, a pronounced saturation is observed for negative . Similar saturation of the transfer characteristics at large gate-biases has been reported in conventional top-gated FETs with top-contacts4, 8, 35. Due to our device geometry, the role played by the back-gate, which modulates the channel but not the contact regions, is analogous to the role played by the top-gate in conventional top-gated TMD FETs (S4 in Supporting Information). Consequently, when = 0 V, the contact regions are highly resistive, and inhibit current flow through the channel, resulting in a low for all . As is progressively made more negative, the contact regions accumulate holes, leading to a decrease of , and in turn, an increase of in the ON state. The saturation is due to dominating the total channel resistance. Since can be modulated much more effectively by , in the ON state is highly sensitive to as compared to . Further, the shift in at the onset of saturation with varying is due to the effect of dual-gating of the channel. A more negative accumulates additional holes in the channel, thereby requiring a more positive to deplete them. The effect is an increase of at the onset of saturation as is made more negative. Finally at = -5 V, the FET remains ON throughout the measured range. The intrinsic nature of WSe is therefore the primary reason why top-gated FETs in the conventional top-contact geometry show poor characteristics8, 21. On the other hand, our structure with back-contacts is better suited for top-gated operation since it allows for efficient top-gate modulation of the contact regions.

Figure 3: (a) Top-gated transfer characteristics of the FET at different values of . (b) The variation of (top-panel), (middle-panel), and (bottom-panel) can be understood qualitatively by considering the effect of on the channel. (c) FET output characteristics show current saturation, and an NDR prior to the onset of saturation. The NDR magnitude changes with , increasing for = -40 V, and gets quenched when = 40 V.

The back-gate can further also be used to tune the FET characteristics. Figure 3(a) shows the top-gated transfer characteristics at different values. Variation in FET parameters like ON current (), , and subthreshold swing () are apparent, and are shown in Figure 3(b). A negative (positive) increases (reduces) the hole density in the channel, leading to a shift. As a consequence, negative (positive) values of reduce (increase) the channel resistance, and increase (reduce) . At negative values of , which increase the channel hole density, the FET turn ON is limited by the contact regions’ turn ON. The relative insensitivity of the contacts to makes insensitive to in this regime. Two predominant regimes are evident in the , at 330 mV/dec for 10 V, and 150 mV/dec for 10 V. For 10 V, the channel is accumulated with excess holes, and the is determined by turn ON of the contact regions. In contrast, for 10 V, the channel is populated with electrons, resulting in a steeper of 150 mV/ dec, dictated by diffusion current from the source to drain34. It is to be noted that the is relatively insensitive to the carrier concentration in the channel, but depends only on the polarity of excess carriers induced by the back-gate.

Figure 3(c) shows the top-gated FET output characteristics at different values of . First, there is a clear evidence of current saturation at large negative for all values of , and . Current saturation is due to channel pinch-off at the drain, similar to a conventional MOSFET. A maximum drive current of 5 A/m is obtained at = -5 V for a long-channel device with = 6 m, which is comparable to values reported for WSe p-FETs with chemically doped source/drain contacts8. Higher drive currents are possible by using shorter channel lengths, and thinner top-gate dielectrics. A second feature is the negative differential resistance (NDR) behavior prior to the onset of current saturation. The NDR behavior that is commonly observed in bulk III-V FETs is due to a transferred electron mechanism, often referred to as the Gunn effect34. Recent reports of NDR in MoS have also been attributed to a transferred electron mechanism between satellite valleys, and/or a self-heating effect36, 37. Our devices, however, also show considerable hysteresis between the forward and reverse - sweeps (S5 in Supporting Information). Both the NDR amplitude, and hysteresis are correlated, increasing for = -40 V, and almost vanishing for = 40 V. The NDR dependence on the value, and polarity suggests that the vertical carrier distribution in the WSe layer plays a key role. Application of changes the position of the charge centroid in the WSe, with negative (positive) shifting the holes closer to (further away from) the SiO substrate. A real space transfer between the high mobility top layer closer to the hBN, and the low mobility bottom layer closer to the SiO substrate could lead to an NDR behavior. The hysteresis dependence on is further suggestive of hot carrier trapping at the WSe-SiO interface29, which increases (decreases) when the carriers are closer to (further away from) the SiO substrate. It is also possible that a transferred electron mechanism could be at play, as evinced by the persistent NDR in both the forward and reverse sweeps, but the hysteresis makes it difficult to unambiguously draw this conclusion.

Figure 4: (a) Low-bias output characteristics showing a mostly linear - behavior, indicating Ohmic nature of the Pt back-contacts even at 2 K. (b) Variation of vs. with temperature shows increasing with reducing temperature for -4 V, characteristic of a metallic phase. The inset shows a close-up of the crossover, at = 39 S ( ). (c) Variation of roughly mirrors , but with a weaker temperature dependence at large negative . The back-gate is grounded for all measurements.

We now proceed to discuss the temperature dependence of transport in our devices. The Ohmic nature of the Pt back-contacts is retained down to 2 K, as shown in Figure 4(a). While the - for small shows a slight non-linearity, the behavior is more linear for large negative , where the channel has a large concentration of holes. This enables use of a standard low-frequency lock-in technique (10 nA excitation at 11.27 Hz) to measure the channel conductivity, = , as a function of temperature (Figure 4(b)). Two distinct regimes are apparent in the temperature variation of ; for -4 V, increases monotonically with decreasing temperature, and for -4 V, does not follow a monotonic trend. The crossover between these two regimes, apparent from Figure 4(b), and Supporting Information S6 suggests a metal-insulator transition (MIT), consistent with previous observations for a variety of 2D electron, and hole systems, including TMDs18, 17, 23, 28. A close-up of the MIT point in the inset of Figure 4(b) shows the crossover at a conductivity = 39 S . Other samples show in the same range of conductivity, albeit with slight variations (S6 in Supporting Information). To better understand the nature of MIT observed in our samples, we discuss the results using the theoretical framework developed to explain the phenomenon in a large set of 2D electron, and hole systems38, 39.

According to the scaling theory of localization, all non-interacting 2D systems exhibit an insulating ground state in the limit of zero temperature40. At high carrier densities, and in samples with reduced disorder, the localization length can exceed the sample size. In this weakly localized state, the 2D system can exhibit an apparent metallic behavior, explained in terms of the temperature dependent screening of fixed charged impurities. For high sample disorder, or at low carrier densities, the system becomes strongly localized, and the temperature dependence of conductivity displays the expected insulating behavior. This crossover from a metallic weakly localized regime at high carrier densities to an insulating strongly localized regime at low carrier densities has been used to explain the MIT in 2D semiconductors38, 17. To ascertain the nature of MIT in our devices, we examine the following temperature scales: the Fermi temperature (), the Bloch-Grüneisen temperature (), and the Dingle temperature () (S7 in Supporting Information). The temperatures , and define scales associated with phonon scattering, and disorder, respectively. An unambiguous manifestation of a weak localization mediated metallic phase requires at the crossover point, a condition which rules out phonon scattering in the metallic phase, and ensures that the disorder is sufficiently weak38. For the sample of Figure 4, = 2,600 cm/Vs, and the crossover carrier density () of 5.3/cm at 2 K, we obtain = 29 K, = 16 K, and = 5.0 K. Since , the temperature dependence of in the metallic phase can potentially be affected by phonon scattering in our devices. We note that in the absence of a more reliable carrier density measurement e.g. through Hall effect, and the uncertainty in , the value of could be underestimated. However, a larger will only increase , and , but still maintain the relation . For acoustic phonon scattering at , is expected to follow a law, resulting in an apparent metallic behavior41. The metallic phase in our devices does not stem solely from a quantum electronic mechanism.

The insulating phase, on the other hand, for , is the expected behavior for a 2D system. While a strong localization effect at low carrier densities results in an insulating behavior, an alternate semiclassical percolation model can also explain this phenomenon39, 20. Density inhomogeneities induced by disorder are believed to block conductive paths in the channel at low carrier densities, leading to an insulating state due to percolation of carriers between the potential fluctuations. The similar values of = expected for both the localization, and percolation mechanisms make it difficult to choose one to explain the insulating phase in our devices, as is the case for other 2D systems38. The variation of vs. , as a function of temperature is shown in Figure 4(c). The variation of roughly resembles , with increasing with reducing temperature for -4 V, and varying weakly for large negative . The weak temperature dependence of when the channel is populated with holes ( -4 V) is consistent with prior reports of contact behavior in MoS FETs18, 27.

Figure 5: Temperature dependence of for three different WSe devices. For 100 K, follows a power law trend, , with the values for the three devices shown in the inset table. At low-temperatures, saturates to 4,000 cm/Vs, limited by Coulomb scattering and/or defects in the WSe. The inset shows variation of with .

Finally, to determine the scattering mechanisms limiting hole transport in WSe, the variation of with temperature in the metallic regime is shown for three different three/four-layer WSe FETs in Figure 5. All three devices show a modest of around 140 cm/Vs at room temperature, which then increases rapidly with decreasing temperature. The variation in the high temperature regime (T 100 K) follows a power law dependence, , with varying values of (from 0.8 to 1.2) for the three samples measured. Acoustic phonon scattering is expected to result in = 1, whereas 1 is a signature of optical phonon scattering being the dominant scattering mechanism41. The values of closer to 1 in our devices suggest that acoustic phonon scattering is the mobility limiting factor42. Lowering of below 1 has been attributed to homopolar phonon quenching by the top-gate dielectric, and/or the collective effect of multiple scattering mechanisms17, 43. At low-temperatures, saturates to an upper limit (), likely limited by Coulomb scattering, or defects41, 44. A critical temperature () can be defined at the crossover of the two regimes of temperature dependence of . There is a considerable variability in between samples ( 800 cm/Vs to 4,000 cm/Vs), which varies inversely with ( 40 K to 7 K), as shown in the inset of Figure 5. The value of can be an indicator of sample quality, with cleaner samples transitioning to a Coulomb scattering dominated transport regime at lower temperatures44. We also note that does not seem to depend on . We attribute the high values of in our devices to the cleaner top hBN-WSe interface, where the holes reside at negative values. The hole mobilities in our devices compare very well with recent reports of electron mobilities in hBN encapsulated WSe45, underlining the high material quality of WSe.

2 Conclusion

To summarize, we successfully used high work-function Pt electrodes to contact the valence band of WSe. Our structure with back-contacts, and an hBN top-gate dielectric provides a device design for optimized top-gated operation, resulting in stable Ohmic p-type contacts without the need for any additional doping of the channel access regions. We observed saturating output characteristics, with signature of a back-gate tunable negative differential resistance. The Ohmic Pt contacts down to cryogenic temperatures enabled us to perform temperature dependent transport measurements which revealed a metal-insulator transition. The temperature dependence of mobility indicated a phonon dominated scattering mechanism at high-temperatures, with a crossover to Coulomb scattering at low-temperatures. Our findings highlight the significance of Pt as a p-type contact for WSe in order to study its intrinsic electrical properties. Moreover, the combination of our back-contact geometry, and an hBN top-gate dielectric provide a viable platform to explore the transport properties of other 2D materials, and their heterostructures.

3 Materials and Methods

3.1 Device Fabrication

The FETs are fabricated using commercially available sources of WSe crystals (HQ Graphene, and nanoScience Instruments). Both source materials result in devices with very similar characteristics. Individual flakes of WSe, and hBN are exfoliated onto 300 nm SiO/Si substrates, and three/four-layer WSe, and 15-20 nm hBN flakes are identified using optical contrast, Raman, and photoluminescence measurements. On a separate substrate, thin Cr/Pt (2 nm/8 nm) electrodes are patterned using a combination of e-beam lithography (EBL), e-beam metal evaporation (EBME), and lift-off. Using a silicone stamp spin-coated with a heat-release polymer30, we first “pick-up” the hBN flake. A custom-built micromanipulator-microscope setup is then used to align, and “pick-up” the WSe using the hBN, resulting in an hBN/WSe stack supported on the polymer. This stack is then aligned, and stamped on to the pre-patterned Cr/Pt electrodes, after which the polymer is washed away in acetone. This leaves the hBN/WSe stack on the Cr/Pt electrodes. A 3 h 200C forming gas (1 Torr) anneal is performed to clean any remaining polymer residues. A local Pd top-gate (30 nm) is then patterned using EBL, EBME, and lift-off. Finally, thick Cr/Au (10 nm/80 nm) contact pads are patterned for electrical probing.

3.2 Electrical Characterization

Room temperature electrical measurements are done in ambient conditions, on a Cascade Summit probe station using an Agilent B1500A DC parameter analyzer. Temperature dependent measurements are done in a PPMS EverCool II Helium refrigerator. An Agilent B1500A is used for DC measurements, and an SR830 lock-in amplifier is used for the low-frequency lock-in measurements.

{acknowledgement}

This work was supported in part by NRI SWAN, Intel Corp., and the NSF NNIN program.

3.3 Supporting Information Available

S1: Raman and photoluminescence characteristics, S2: Transfer characteristics and top-gate leakage, S3: 2-point and 4-point measurement scheme, S4: Top-contacts vs back-contacts, S5: Hysteresis in output characteristics, S6: Metal-insulator transition, S7: Temperature scales for MIT.

Supporting Information

4 S1: Raman and photoluminescence characteristics

Figure S1: (a) Raman spectrum of a typical exfoliated three/four-layer WSe flake, with the peaks labeled. (b) The PL spectrum shows two peaks arising from the direct, and indirect transitions.

Figure S1 shows the Raman and photoluminescence (PL) spectra of a typical three/four-layer exfoliated WSe flake, measured using a 532 nm laser excitation. The sharp Raman peaks shown in Figure S1(a) reflect the good material quality of the flakes used in this work. The full width at half maximum for the A peak is 3 cm indicating high in-plane crystallinity46. This is further corroborated by the PL spectrum shown in Figure S1(b). The two distinct peaks correspond to the direct bap transition at 1.62 eV, and the indirect gap transition at 1.46 eV29.

5 S2: Transfer characteristics and top-gate leakage

Figure S2: (a) Top-gated transfer characteristics of the FET on a linear scale. (b) The top-gate leakage current stays at the noise-floor throughout the measurement range.

Figure S2(a) shows the top-gated transfer characteristics of the FET plotted on a linear scale. A threshold voltage () -2 V can be extracted by extrapolating the linear region to the top-gate voltage () axis. The top-gate leakage is shown in Figure S2(b), which stays at the noise-floor of the measurement setup throughout the range of probed.

6 S3: 2-point and 4-point measurement scheme

Figure S3: The biasing scheme used for measurement of and . The scale bars are 10 m.

Figure S3 shows the biasing scheme used for measurement of the 2-point conductance (), and intrinsic, 4-point conductance (). For measuring , a pair of adjacent contacts are used as the source and drain, and = /. To measure between the same two contacts, an outer pair of contacts are chosen as the source and drain. The voltage drop between the original pair of contacts (-) is then measured with a current () flowing through the outer pair of contacts. Now, = /(-).

7 S4: Top-contacts vs back-contacts

Figure S4: (a) Schematic of our dual-gated FET structure with back-contacts. (b) Schematic of conventional TMD FETs with top-contacts.

Figures S4(a), and (b) show the schematics of our FET structure with back-contacts, and a conventional FET with top-contacts, respectively. The field lines from the top-gate are represented by white arrows, and the field lines from the back-gate by black arrows. In Figure S4(a), the top-gate is able to modulate the channel, the contact regions, and the channel access regions. Field lines from the back-gate, however, are screened out by the Pt back-contacts (shown by red crosses). Back-gated transfer characteristics are therefore severely contact resistance dominated. In contrast, for a conventional top-contact geometry (Figure S4(b)), the top-gate is unable to modulate the contact regions due to screening by the top-contact electrodes. Consequently, the top-gated transfer characteristics display a similar series resistance limited behavior4, 47, 8. Placing contacts underneath the flake optimizes our structure for top-gated operation.

8 S5: Hysteresis in output characteristics

Figure S5: Forward and reverse - sweeps show hysteresis at the NDR point, which reduces with the application of a positive .

Figure S5 shows the forward and reverse sweeps of the FET output characteristics at different values of . A negative differential resistance (NDR), and a corresponding hysteresis near the NDR region are apparent. The hysteresis is negligible both for low , and large negative . Both the NDR, and hysteresis increase (decrease) for negative (positive) , suggestive of hot carrier trapping at the WSe-SiO interface29. It is to be noted that negligible carrier trapping at low indicates clean interfaces for low energy holes. Only hot holes generated at a sufficiently large negative can overcome the potential barrier to enter a trap state.

9 S6: Metal-insulator transition

Figure S6: Conductivity temperature dependence for two other devices. A clear insulating state for low is apparent for both devices in the log scale (right-top, and right-bottom panels)

Figure S6 shows temperature dependence of for two other representative devices. The data for the device in Figure S6(a) shows a broad MIT crossover in the range of . A clear insulating state is observed for -2.5 V. The device in Figure S6(b) shows a crossover point developing at = -7 V, at 2, similar to a prior report on monolayer WSe23. The oscillatory behavior of at low-temperatures is indicative of disorder, and charge puddles which cause mesoscopic fluctuations with varying 48.

10 S7: Temperature scales for MIT

Figure S7: Close up of the MIT crossover for two devices. The device in (a) has = 2,600 cm/Vs, and the device in (b) has = 800 cm/Vs.

Figure S7 shows the MIT crossover for two WSe devices, with the crossover voltage (), and marked. The carrier density at crossover () can then be calculated using , where is the electron charge. Three different temperature scales can then be defined according to ref.38 as - the electron temperature scale defined by the Fermi temperature (), the phonon temperature scale defined by the Bloch-Grüneisen temperature (), and the disorder temperature scale defined by the Dingle temperature (), as follows:

(S1)
(S2)
(S3)

Here, is the Fermi energy, is the Fermi wave vector, is the carrier effective mass, is the phonon velocity, is the impurity-scattering induced level broadening, and is the carrier mobility. We assume a spin-degeneracy of 2, and a valley degeneracy of 1 for relating and , , where is the free electron mass, and = 6 m/s is the phonon velocity41, 49. is the Boltzmann constant, and is the reduced Planck constant.

For the device in Figure S7(a), = 5.3/cm, and = 2,600 cm/Vs at 2 K. We therefore calculate = 29 K, = 16 K, and = 5.0 K at the crossover point.

For the device in Figure S7(b), with = 1.1/cm, and = 800 cm/Vs at 10 K, we calculate = 62 K, = 24 K, and = 17 K. We find even for this device, indicating a phonon scattering effect to be the cause of the metallic behavior.

It is to be noted that given the lack of Hall measurements, and the uncertainty in , the value of used for calculating , and could be underestimated. However, even when considering the extreme case of = 0 V for the device in Figure S7(a), we obtain = 3.7/cm, which increases , and to = 200 K, and = 42 K. Since depends only on the mobility, it remains unchanged. The relation is maintained even in this case.

References

  • Geim and Grigorieva 2013 Geim, A. K.; Grigorieva, I. V. Van der Waals Heterostructures. Nature 2013, 499, 419–425.
  • Chhowalla et al. 2013 Chhowalla, M.; Shin, H. S.; Eda, G.; Li, L.-J.; Loh, K. P.; Zhang, H. The Chemistry of Two-Dimensional Layered Transition Metal Dichalcogenide Nanosheets. Nat. Chem. 2013, 5, 263–275.
  • Jariwala et al. 2014 Jariwala, D.; Sangwan, V. K.; Lauhon, L. J.; Marks, T. J.; Hersam, M. C. Emerging Device Applications for Semiconducting Two-Dimensional Transition Metal Dichalcogenides. ACS Nano 2014, 8.
  • Radisavljevic et al. 2011 Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, V.; Kis, A. Single-Layer MoS Transistors. Nat. Nanotechnol. 2011, 6, 147–150.
  • Das et al. 2013 Das, S.; Chen, H.-Y.; Penumatcha, A. V.; Appenzeller, J. High Performance Multilayer MoS Transistors with Scandium Contacts. Nano Lett. 2013, 13, 100–105.
  • Larentis et al. 2012 Larentis, S.; Fallahazad, B.; Tutuc, E. Field-Effect Transistors and Intrinsic Mobility in Ultra-Thin MoSe Layers. Appl. Phys. Lett. 2012, 101.
  • Sik Hwang et al. 2012 Sik Hwang, W.; Remskar, M.; Yan, R.; Protasenko, V.; Tahy, K.; Doo Chae, S.; Zhao, P.; Konar, A.; (Grace) Xing, H.; Seabaugh, A. et al. Transistors with Chemically Synthesized Layered Semiconductor WS Exhibiting 10 Room Temperature Modulation and Ambipolar Behavior. Appl. Phys. Lett. 2012, 101.
  • Fang et al. 2012 Fang, H.; Chuang, S.; Chang, T. C.; Takei, K.; Takahashi, T.; Javey, A. High-Performance Single Layered WSe p-FETs with Chemically Doped Contacts. Nano Lett. 2012, 12, 3788–3792.
  • Liu et al. 2013 Liu, W.; Kang, J.; Sarkar, D.; Khatami, Y.; Jena, D.; Banerjee, K. Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe Field Effect Transistors. Nano Lett. 2013, 13, 1983–1990.
  • Das and Appenzeller 2013 Das, S.; Appenzeller, J. WSe Field Effect Transistors with Enhanced Ambipolar Characteristics. Appl. Phys. Lett. 2013, 103.
  • Podzorov et al. 2004 Podzorov, V.; Gershenson, M. E.; Kloc, C.; Zeis, R.; Bucher, E. High-Mobility Field-Effect Transistors Based on Transition Metal Dichalcogenides. Appl. Phys. Lett. 2004, 84, 3301–3303.
  • Ross et al. 2014 Ross, J. S.; Klement, P.; Jones, A. M.; Ghimire, N. J.; Yan, J.; D. G. Mandrus, T. T., and; Watanabe, K.; Kitamura, K.; Yao, W.; Cobden, D. H. et al. Electrically Tunable Excitonic Light-Emitting Diodes Based on Monolayer WSe p-n Junctions. Nat. Nanotechnol. 2014, 9, 268–272.
  • Mak et al. 2014 Mak, K. F.; McGill, K. L.; Park, J.; McEuen, P. L. The Valley Hall Effect in MoS Transistors. Science 2014, 344, 1489–1492.
  • Xiao et al. 2012 Xiao, D.; Liu, G.-B.; Feng, W.; Xu, X.; Yao, W. Coupled Spin and Valley Physics in Monolayers of and Other Group-VI Dichalcogenides. Phys. Rev. Lett. 2012, 108, 196802.
  • Banerjee et al. 2009 Banerjee, S. K.; Register, L.; Tutuc, E.; Reddy, D.; MacDonald, A. Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device. IEEE Electron Device Lett. 2009, 30, 158–160.
  • Fogler et al. 2014 Fogler, M. M.; Butov, L. V.; Novoselov, K. S. High-Temperature Superfluidity with Indirect Excitons in van der Waals Heterostructures. Nat. Commun. 2014, 5.
  • Radisavljevic and Kis 2013 Radisavljevic, B.; Kis, A. Mobility Engineering and a Metal-Insulator Transition in Monolayer MoS. Nat. Mater. 2013, 12, 815–820.
  • Baugher et al. 2013 Baugher, B. W. H.; Churchill, H. O. H.; Yang, Y.; Jarillo-Herrero, P. Intrinsic Electronic Transport Properties of High-Quality Monolayer and Bilayer MoS. Nano Lett. 2013, 13, 4212–4216.
  • Jariwala et al. 2013 Jariwala, D.; Sangwan, V. K.; Late, D. J.; Johns, J. E.; Dravid, V. P.; Marks, T. J.; Lauhon, L. J.; Hersam, M. C. Band-Like Transport in High Mobility Unencapsulated Single-Layer MoS Transistors. Appl. Phys. Lett. 2013, 102.
  • Chen et al. 2014 Chen, X.; Wu, Z.; Xu, S.; Wang, L.; Huang, R.; Han, Y.; Ye, W.; Xiong, W.; Han, T.; Long, G. et al. Probing the Electron States and Metal-Insulator Transition Mechanisms in ​Molybdenum Disulphide Vertical Heterostructures. Nat. Commun. 2014, 6.
  • Wang et al. 2015 Wang, J. I.-J.; Yang, Y.; Chen, Y.-A.; Watanabe, K.; Taniguchi, T.; Churchill, H. O. H.; Jarillo-Herrero, P. Electronic Transport of Encapsulated Graphene and WSe Devices Fabricated by Pick-up of Prepatterned hBN. Nano Lett. 2015, 15, 1898–1903.
  • Pradhan et al. 2014 Pradhan, N. R.; Rhodes, D.; Memaran, S.; Poumirol, J. M.; D. Smirnov, S. T. a. S. F., and; Perea-Lopez, N.; Elias, A. L.; Terrones, M.; Ajayan, P. M.; Balicas, L. Hall and Field-Effect Mobilities in Few Layered p-WSe Field-Effect Transistors. Sci. Rep. 2014, 5.
  • Allain and Kis 2014 Allain, A.; Kis, A. Electron and Hole Mobilities in Single-Layer WSe. ACS Nano 2014, 8, 7180–7185.
  • Pradhan et al. 2014 Pradhan, N. R.; Rhodes, D.; Feng, S.; Xin, Y.; Memaran, S.; Moon, B.-H.; Terrones, H.; Terrones, M.; Balicas, L. Field-Effect Transistors Based on Few-Layered -MoTe. ACS Nano 2014, 8, 5911–5920.
  • Li et al. 2014 Li, L.; Yu, Y.; Ye, G. J.; Ge, Q.; Ou, X.; Wu, H.; Feng, D.; Chen, X. H.; Zhang, Y. Black Phosphorus Field-Effect Transistors. Nat. Nanotechnol. 2014, 9, 372–377.
  • Chuang et al. 2014 Chuang, S.; Battaglia, C.; Azcatl, A.; McDonnell, S.; Kang, J. S.; Yin, X.; Tosun, M.; Kapadia, R.; Fang, H.; Wallace, R. M. et al. MoS P-type Transistors and Diodes Enabled by High Work Function MoO Contacts. Nano Lett. 2014, 14.
  • Cui et al. 2015 Cui, X.; Lee, G.-H.; Kim, Y. D.; Arefe, G.; Huang, P. Y.; Lee, C.-H.; Chenet, D. A.; Zhang, X.; Wang, L.; Ye, F. et al. Multi-Terminal Electrical Transport Measurements of MoS Using a van der Waals Heterostructure Device Platform. Nat. Nanotechnol. 2015, 534–540.
  • Chuang et al. 2014 Chuang, H.-J.; Tan, X.; Ghimire, N. J.; Perera, M. M.; Chamlagain, B.; Cheng, M. M.-C.; Yan, J.; Mandrus, D.; Tománek, D.; Zhou, Z. High Mobility WSe p- and n-Type Field-Effect Transistors Contacted by Highly Doped Graphene for Low-Resistance Contacts. Nano Lett. 2014, 14, 3594–3601.
  • Kim et al. 2015 Kim, K.; Larentis, S.; Fallahazad, B.; Lee, K.; Xue, J.; Dillen, D. C.; Corbet, C. M.; Tutuc, E. Band Alignment in WSe-Graphene Heterostructures. ACS Nano 2015, 9, 4527–4532.
  • Wang et al. 2013 Wang, L.; Meric, I.; Huang, P. Y.; Gao, Q.; Gao, Y.; Tran, H.; Taniguchi, T.; Watanabe, K.; Campos, L. M.; Muller, D. A. et al. One-Dimensional Electrical Contact to a Two-Dimensional Material. Science 2013, 342, 614–617.
  • Singh-Miller and Marzari 2009 Singh-Miller, N. E.; Marzari, N. Surface Energies, Work Functions, and Surface Relaxations of Low-Index Metallic Surfaces from First Principles. Phys. Rev. B 2009, 80.
  • Gong et al. 2013 Gong, C.; Huang, C.; Miller, J.; Cheng, L.; Hao, Y.; Cobden, D.; Kim, J.; Ruoff, R. S.; Wallace, R. M.; Cho, K. et al. Metal Contacts on Physical Vapor Deposited Monolayer MoS. ACS Nano 2013, 7, 11350–11357.
  • Roy et al. 2015 Roy, T.; Tosun, M.; Cao, X.; Fang, H.; Lien, D.-H.; Zhao, P.; Chen, Y.-Z.; Chueh, Y.-L.; Guo, J.; Javey, A. Dual-Gated MoS/WSe van der Waals Tunnel Diodes and Transistors. ACS Nano 2015, 9, 2071–2079.
  • Streetman and Banerjee 2005 Streetman, B.; Banerjee, S. Solid State Electronic Devices; Prentice Hall, 2005.
  • Sanne et al. 2015 Sanne, A.; Ghosh, R.; Rai, A.; Movva, H. C. P.; Sharma, A.; Rao, R.; Mathew, L.; Banerjee, S. K. Top-Gated Chemical Vapor Deposited MoS Field-Effect Transistors on SiN Substrates. Appl. Phys. Lett. 2015, 106.
  • Li et al. 2015 Li, X.; Yang, L.; Si, M.; Li, S.; Huang, M.; Ye, P.; Wu, Y. Performance Potential and Limit of MoS Transistors. Adv. Mater. 2015, 27, 1547–1552.
  • Serov et al. 2014 Serov, A.; Dorgan, V.; English, C.; Pop, E. Multi-Valley High-Field Transport in 2-Dimensional MoS Transistors. Device Research Conference (DRC), 2014 72nd Annual 2014, 183–184.
  • Das Sarma and Hwang 2014 Das Sarma, S.; Hwang, E. H. Two-Dimensional Metal-Insulator Transition as a Strong Localization Induced Crossover Phenomenon. Phys. Rev. B 2014, 89, 235423.
  • Das Sarma et al. 2013 Das Sarma, S.; Hwang, E. H.; Li, Q. Two-Dimensional Metal-Insulator Transition as a Potential Fluctuation Driven Semiclassical Transport Phenomenon. Phys. Rev. B 2013, 88, 155310.
  • Abrahams et al. 1979 Abrahams, E.; Anderson, P. W.; Licciardello, D. C.; Ramakrishnan, T. V. Scaling Theory of Localization: Absence of Quantum Diffusion in Two Dimensions. Phys. Rev. Lett. 1979, 42, 673–676.
  • Kaasbjerg et al. 2012 Kaasbjerg, K.; Thygesen, K. S.; Jacobsen, K. W. Phonon-Limited Mobility in -type Single-Layer MoS From First Principles. Phys. Rev. B 2012, 85, 115317.
  • Kaasbjerg et al. 2013 Kaasbjerg, K.; Thygesen, K. S.; Jauho, A.-P. Acoustic Phonon Limited Mobility in Two-Dimensional Semiconductors: Deformation Potential and Piezoelectric Scattering in Monolayer MoS from First Principles. Phys. Rev. B 2013, 87, 235312.
  • Schmidt et al. 2014 Schmidt, H.; Wang, S.; Chu, L.; Toh, M.; Kumar, R.; Zhao, W.; Castro Neto, A. H.; Martin, J.; Adam, S.; Ozyilmaz, B. et al. Transport Properties of Monolayer MoS Grown by Chemical Vapor Deposition. Nano Lett. 2014, 14, 1909–1913.
  • Ma and Jena 2014 Ma, N.; Jena, D. Charge Scattering and Mobility in Atomically Thin Semiconductors. Phys. Rev. X 2014, 4, 011043.
  • Xu et al. 2015 Xu, S.; Han, Y.; Long, G.; Wu, Z.; Chen, X.; Han, T.; Ye, W.; Lu, H.; Wu, Y.; Lin, J. et al. High-Quality BN/WSe/BN Heterostructure and its Quantum Oscillations. arXiv preprint arXiv:1503.08427 2015,
  • Zhao et al. 2013 Zhao, W.; Ghorannevis, Z.; Amara, K. K.; Pang, J. R.; Toh, M.; Zhang, X.; Kloc, C.; Tan, P. H.; Eda, G. Lattice Dynamics in Mono- and Few-Layer Sheets of WS and WSe. Nanoscale 2013, 5, 9677–9683.
  • Wang et al. 2012 Wang, H.; Yu, L.; Lee, Y.-H.; Shi, Y.; Hsu, A.; Chin, M. L.; Li, L.-J.; Dubey, M.; Kong, J.; Palacios, T. Integrated Circuits Based on Bilayer MoS Transistors. Nano Lett. 2012, 12, 4674–4680.
  • Ghatak et al. 2011 Ghatak, S.; Pal, A. N.; Ghosh, A. Nature of Electronic States in Atomically Thin MoS Field-Effect Transistors. ACS Nano 2011, 5, 7707–7712.
  • Kumar and Ahluwalia 2012 Kumar, A.; Ahluwalia, P. Electronic Structure of Transition Metal Dichalcogenides Monolayers 1H-MX (M = Mo, W; X = S, Se, Te) from Ab-Initio Theory: New Direct Band Gap Semiconductors. Eur. Phys. J. B 2012, 85.
Comments 0
Request Comment
You are adding the first comment!
How to quickly get a good reply:
  • Give credit where it’s due by listing out the positive aspects of a paper before getting into which changes should be made.
  • Be specific in your critique, and provide supporting evidence with appropriate references to substantiate general statements.
  • Your comment should inspire ideas to flow and help the author improves the paper.

The better we are at sharing our knowledge with each other, the faster we move forward.
""
The feedback must be of minimum 40 characters and the title a minimum of 5 characters
   
Add comment
Cancel
Loading ...
174589
This is a comment super asjknd jkasnjk adsnkj
Upvote
Downvote
""
The feedback must be of minumum 40 characters
The feedback must be of minumum 40 characters
Submit
Cancel

You are asking your first question!
How to quickly get a good answer:
  • Keep your question short and to the point
  • Check for grammar or spelling errors.
  • Phrase it like a question
Test
Test description