Design and Electronics Commissioning of the Physics Prototype of a Si-W Electromagnetic Calorimeter for the International Linear Collider
The CALICE collaboration is studying the design of high performance electromagnetic and hadronic calorimeters for future International Linear Collider detectors. For the electromagnetic calorimeter, the current baseline choice is a high granularity sampling calorimeter with tungsten as absorber and silicon detectors as sensitive material. A “physics prototype” has been constructed, consisting of thirty sensitive layers. Each layer has an active area of cm and a pad size of cm. The absorber thickness totals 24 radiation lengths. It has been exposed in 2006 and 2007 to electron and hadron beams at the DESY and CERN beam test facilities, using a wide range of beam energies and incidence angles. In this paper, the prototype and the data acquisition chain are described and a summary of the data taken in the 2006 beam tests is presented. The methods used to subtract the pedestals and calibrate the detector are detailed. The signal-over-noise ratio has been measured at . Some electronics features have been observed; these lead to coherent noise and crosstalk between pads, and also crosstalk between sensitive and passive areas. The performance achieved in terms of uniformity and stability is presented.
- 1 ECAL Si-W physics prototype
- 2 Electronics and data acquisition
- 3 Beam tests
4 Pedestal, noise, and crosstalk around module edge
- 4.1 Pedestal subtraction procedure
- 4.2 Uniformity and stability of the residual pedestals and noise
- 4.3 Crosstalk around the module edge
- 5 Calibration of the detector
1 ECAL Si-W physics prototype
The CALICE (Calorimetry for the Linear Collider Experiments) collaboration  is studying several designs of calorimeters for experiments at the future International Linear Collider (ILC) . In order to have a mature design when the first results from the Large Hadron Collider experiments are expected and decisions on future colliders made, two main development phases have been defined. In the first phase, characterised by the construction of “physics prototypes”, the feasibility of building a pixelised calorimeter is studied. In the second phase, “technological prototypes” will focus on the engineering details needed to insert such a calorimeter in an ILC detector. In both phases, the prototypes will be subject to extensive studies at beam test facilities. The data acquisition (DAQ) chain is common to all calorimeters, thereby easing their integration. The physics prototype for the electromagnetic calorimeter (ECAL) described in this document is a high granularity silicon-tungsten sampling calorimeter. Whereas the proof-of-principle of such detector has already been proven e.g. at LEP   and SLD , the challenge for an ILC detector is the much larger size and the compactness required.
Physics at the ILC places stringent requirements on the detector , including the ability to measure jet energies with a precision of at least
1.1 Physics considerations driving the design
With a sampling calorimeter approach, the choice of absorber material is driven by the need to separate particles in a jet and the need for a compact calorimeter. Separation of particles in the transverse direction requires an absorber material which gives narrow electromagnetic (EM) showers and so needs to have a small Molière radius. Separation longitudinally requires a material with short EM showers, which pushes for a material with a small radiation length (X). The same requirement also results in a compact ECAL. Tungsten is such a material, with a Molière radius of 9 mm, and a radiation length of 3.5 mm. Furthermore, the ratio of interaction length to radiation length is 27.4 so that hadronic showers typically develop later than EM showers. For the physics prototype, the pad size is cm, comparable to the Molière radius. The choice of high resistivity silicon as the active material is motivated by the requirements of granularity and compactness. To contain high energy showers, the prototype should have around 24 X in total; this will ensure a containment of 99.5 % of the energy for 5 electron showers, and better than 98 % for 50 showers. Thirty layers were chosen to provide sufficient granularity. A small tungsten thickness in the first layers ensures a good energy resolution at low energy.
1.2 Geometry and mechanical structure
At normal incidence, the prototype has a total depth of 24 radiation lengths, achieved using 10 layers of 0.4 X (1.4 mm) thick tungsten absorber plates, followed by 10 layers of 0.8 X (2.8 mm) thick plates, and another 10 layers of 1.2 X (4.2 mm) thick plates, with an overall thickness of 20 cm. Each silicon layer has an active area of cm, segmented into modules of readout pads of cm each. The active volume of the physics prototype therefore consists of 30 layers of modules, giving in total 9720 channels.
The design and construction of the prototype presents a number of engineering challenges. A particular innovative effort has been made to minimise passive material zones and to keep the calorimeter as compact as possible, by incorporating half of the tungsten into alveolar composite structures. Three independent structures can be distinguished, as shown in Figure 2, one for each thickness of tungsten. Each structure is fabricated by moulding preimpregnated carbon fibre (Cfi) and epoxy (“prepreg”) onto tungsten sheets, leaving free spaces between two layers to insert the detection units, called detector slabs.
One detector slab, shown in Figure 2, consists of two active readout layers mounted on each side of an H-shaped supporting structure. The slab is shielded on both sides from the tungsten alveolar structure by an aluminium foil 0.1 mm thick, to protect the silicon modules from electromagnetic noise and provide the wafer substrate ground. The H-shaped structure is 326 mm long and 125.6 mm wide, and has a mass of either 1.1, 2.2 or 3.3 kg depending on the tungsten thickness. The active layer is made of a 14-layer printed circuit board (PCB), 2.1 mm thick and 600 mm long, holding high resistivity silicon wafers 525 m thick (see Section 1.3). The wafers are cut into square modules of mm, separated from each other by a 0.15 mm wide mounting gap.
Two detector slabs are inserted per layer, into the central and bottom cells of the alveolar structure (see Figure 2). The central and bottom slab active areas are formed by an array of modules and a row of 3 modules respectively. To reduce overlapping passive areas, the two
The passive area between modules is mainly due to two 1 mm wide guard rings around the modules (see Section 1.3). A larger passive area is located between the central and bottom slabs, and includes the two guard rings, two 0.15 mm wide mounting gaps between module and PCB, two 0.3 mm thick H structures, two 0.1 mm thick aluminium shields, a 0.3 mm wide global mounting gap, and a 0.4 mm thick composite sheet, giving a total of 3.8 mm.
All the composite parts, i.e. H-shaped and alveolar structures, are made using 0.15 mm thick carbon fibre and epoxy prepreg, TEXIPREG® CC120 ET443 , with an average thickness of 0.15 mm.
Each alveolar structure is made in a single curing step of four hours at 135C. Fifteen metal cores are used to form the alveoli. They are wrapped with one layer of composite, and alternated with tungsten layers to obtain the final structure. Since the thermal expansion coefficient of carbon fibre is very close to that of tungsten, distortions during the curing are small. After curing, the metal cores are taken out, leaving empty spaces for the detector slabs (see Figure 5).
The thin composite sheets located between two cells consist of three composite layers of thickness 0.4 mm. Dimension and geometry tolerances of the structure are directly dependent on the machining of the mould: all pieces were ground with a resulting flatness of mm. Metallic inserts, also included in the composite structure, are used to fasten each structure on its support table.
The mechanical and electrical connection of the silicon pads to the PCB is made using EPO-TEK® 4110 conductive glue . For the central (bottom) slabs, 216 (108) spots of conducting glue are deposited on each PCB by a pneumatically driven syringe dispenser, mounted on an X-Y automatic robot. The low viscosity nature of the gluing paste keeps the spots correctly shaped during the process. The pressure and the deposit time were chosen to obtain a final spot size between 3 and 4 mm in diameter. The thickness of the glue is calibrated by using nylon spacers 0.12 mm thick. Then, the six (three) modules for the central (bottom) slabs are put on the PCB by hand, as shown in Figure 5. The accurate positioning of each module is ensured during the polymerisation cycle by a grid of tungsten wires, holding the wafers in place. The expected accuracy is mm, arising from the average module size of 61.95 mm and the 62.05 mm imposed by the grid of wires.
The curing process is fundamental to the performance of the connection. Curing parameters were chosen to have a good compromise between the final resistance of the connection () and the mechanical stress applied on the spots of glue. The latter is due to the differential thermal expansion between the PCB and the silicon. The polymerisation of the glue was therefore done at C for twelve hours.
Beam test configurations
To test the physics behaviour of the ECAL prototype with different impact angles of the beam, a rotational support was designed with six discrete angular configurations, from to . The position of the three independent alveolar structures can be adjusted according to the chosen angle, to ensure the primary particle will travel through the centre of the active area, as shown in Figure 6. Each structure is mounted on rails, positioned manually and fixed using mechanical pins, with a precision of 0.5 mm, giving an error of on the angle. The main error on the angle arises from the manual placement of the ECAL compared to the beam, and is .
In order to vary the impact position of the primary particle on the detector surface, the mechanical support of the prototype has been equipped with a control system allowing for a motion along both the ( mm) and ( mm) axes, with a precision of mm. The position can be piloted remotely during beam operation.
1.3 Description of the sensitive area
The sensors are made from four inch diameter silicon wafers. A resistivity greater than 5 k cm is necessary to ensure a full depletion with a reasonable bias voltage, and to obtain low bulk leakage currents. A wafer thickness of 525 m was chosen, to obtain a signal-to-noise ratio of about 10 at the end of the whole readout electronics chain. The noise of the readout electronics results from the capacitance of the pad itself, the capacitance of the line on the PCB, and
the preamplifier noise. A minimum ionising particle (MIP) produces about 80 electron-hole pairs per m of silicon, hence 42,000 electrons are obtained for the 525 m thickness, giving an allowable noise range for the readout electronics of up to 4000 electrons. The crystallographic orientation of the silicon () has only little importance; the detection of EM showers instead of single particles ensures that the fraction of energy lost through “channeling effects” is very small compared to the total signal.
Each wafer is used to make a module, consisting of a matrix of PIN diodes (pads) of 1 cm, as shown in Figure 7. The overall dimensions take into account the guard rings. The anode side (N) is common to all pads. The PIN structure is made with ionic implantation. In order to keep the price and the rate of rejected processed modules low, the manufacturing must be as simple as possible, with a minimum number of steps during processing. The final detector will need about 3000 m of such detectors. The passivation layer of the processed module must be compatible with the gluing process described in Section 1.2.1. The main characteristics of a module are presented in Table 1.
|Wafer diameter||4 inch||Capacitance per pad||21 pF|
|Wafer resistivity||5 k cm||Full depletion bias voltage||150 V|
|Wafer thickness||m||Nominal operating bias voltage||200 V|
|MIP deposit||42 000 electrons||Break down voltage||V|
|Average tile side||mm||Leakage current at 200 V||nA (full matrix)|
Module test setup and results
Silicon PIN diode matrices are a priori very simple detectors. Having a whole ECAL covered with high resistivity silicon is however challenging, and implies the necessity to control the process at the earliest stage, in particular in terms of passivation. Therefore several manufacturers were used, enabling testing and validation of several technologies necessary to optimise the production in the future, and minimizing the cost.
For the physics prototype, 270 modules are needed. The production of the modules extended from January 2003 to June 2007. All modules are made of raw wafers produced by Wacker . The modules were produced by two manufacturers: the Institute of Nuclear Physics, Moscow State University , and ON Semiconductor Czech Republic  in conjunction with the Institute of Physics, Academy of Sciences of the Czech Republic, Prague.
The two manufacturers use the same basic technique of ion implantation. Guard rings 1 mm thick have been designed around the matrices to reduce surface leakage currents, with two different geometries. For both, the edge termination is made using the floating guard rings technique  which does not require any extra step in the fabrication process of modules, helping to reduce the overall cost.
Before gluing, the modules are characterised one-by-one by measuring the leakage current as a function of bias voltage (I-V curve), the full depletion voltage (C-V curve) and the stability in time (leakage current versus time at nominal bias). If measurements are taken with a single biased pad, the values are found not to be representative of the performance of the module, especially in terms of breakdown voltage. All 36 pads are therefore biased, using a box specifically designed with 36 contacts made to the module using pin sensors mounted on springs, so as not to damage the surface. Two representative I-V curves taken with this setup are shown in Figure 8.
The test bench was used to characterise 550 modules, with an overall yield of 54 %. Wafers were rejected if the full depletion voltage was greater than 150 V, or if the breakdown voltage was less than 400 V, or if the sum of the leakage currents of all 36 pads at the nominal operation voltage of 200 V was greater than 350 nA.
Calibration of the slabs
Once validated, the modules were assembled by gluing onto PCBs. Before assembling into a slab, the PCBs were tested in pairs using a cosmic-ray muon test bench, with a dedicated DAQ system. The gluing of each pad and the proper contact with the aluminum foil were checked and a first calibration of each half module, associated with a common readout chip (see Section 2.1), was possible. Initial MIP calibration results for each half module are obtained with a precision of approximately 5 %. An example is shown in Figure 9.
On average, the signal-to-noise ratio is measured to be , with a standard deviation of , and less than 0.1 % of the channels are identified as being dead. The quality of the points of glue can be estimated from the noise, since the measured noise increases with the resistivity of the contact point. The chemical passivation of some modules was found not to withstand the gluing process; it was found that the leakage current became greater than 10 A per module. This problem has now been solved by the producer.
The first slab was assembled in September 2004. Since that time, there has been no evidence of a degradation of the noise due to the gluing process.
2 Electronics and data acquisition
The very-front-end (VFE) ASICs used to read out the silicon modules have been specifically designed for the prototype and are called FLC_PHY3. The outputs of the VFE ASICs are transmitted to the off-detector electronics using differential analogue lines. The analogue-to-digital conversion is done on off-detector VME boards, using 16-bits ADCs. Each VME board can read out 96 VFE ASICs, and store the digitised data in memory for subsequent readout by an online software system written in C++.
2.1 On-detector readout electronics
The FLC_PHY3 VFE chip is an 18 channel, charge sensitive, front end circuit. It provides a shaped signal proportional to the input charge. Two chips are hence necessary to read out one module. Having two chips per module also introduces a redundancy into the system by decorrelating ASIC and module behaviour.
Each channel is made of a variable gain charge preamplifier followed by two parallel shaping filters of different gain (1 and 10) using a CR-RC shaper, as shown in Figure 10. Each of these shapers is followed by a sample & hold device (referred to as “T&Hold” in Figure 10) driving a single multiplexed output. The bias of each stage is common to all channels.
The forward path of the preamplifier consists of an input PMOS transistor used in a common source configuration, ensuring a high transconductance. It is followed by a folded cascade bipolar NPN component. The last stage is made of a PMOS follower. The feedback is made with a switchable capacitance allowing a total feedback from 0.2 pF to 3 pF in steps of 0.2 pF. The DC resistive feedback is ensured by a series of unbalanced current mirrors faking a 22.5 M resistor. This keeps the parallel noise negligible at the working frequency.
The shaper is made of a differential input and a single ended output amplifier with an open loop gain of around 100. The filter is a first order active pass-band with a frequency centred at around 1 MHz and a peaking time of 200 ns. This value has been chosen as a trade-off between the serial noise of the preamplifier which performs the optimal shaping around 1 s, the trigger latency which forbids a peaking time faster than 150 ns, and the counting rates imposed by the ILC beam structure which require a recovery time below 300 ns to avoid dead time on a pad. The sample & hold is ensured by a 2 pF capacitance followed by a buffer using a Widlar structure.
The preamplifier gain is obtained with a nominal feedback capacitance of 1.6 pF allowing a maximum input signal of around 4 pC, equivalent to 600 MIPs. A non-linearity of below 0.3 % up to 500 MIPs is achieved, as shown in Figure 11, and summarised in Table 2. The residuals for the obvious non-linear regions above 3.27 pC (0.3 pC) for gain 1 (10) are not shown. In Monte Carlo (MC) simulation and beam test data of a 45 shower, the observed rate of hits recording more than 500 MIPs is about one hit per 500 events. In 100 shower however, the MC simulation predicts about 3.3 hits per event with energy deposit greater than 500 MIPs. This issue will be addressed in the next version of the chip .
|Qinj max||3.27 pC||0.33 pC|
|Vout max||1.27 V (over 50 )||1.12 V (over 50 )|
|Preamplifier Gain||391 mV pC||3.44 V pC|
|Measured Feedback capacitance||1.27 pF||1.45 pF|
|Non-linearity||0.32 %||0.36 %|
The equivalent charge for the noise has been measured on the VFE chip at around 4000 electrons, i.e. 0.1 MIP, with an input capacitance of 80 pF. This capacitance is made up of the detector capacitance of 20 pF added to the PCB line capacitance of 60 pF. The dynamic range hence goes from 0.1 MIP to 600 MIP, thus 13 bits using one shaper gain. The use of the two gains on the shaper in principle increases the dynamic range to 15 bits, although the high gain option was not used for the studies presented here.
From charge-injection measurements, the electronics crosstalk between adjacent channels is found to be less than 0.1 %.
The consumption of the whole chip is 150 mW corresponding to 8.3 mW dissipation per channel. It would be easy to reduce that consumption by reducing the input transistor bias current, depending on the noise yield and the input capacitance. Setting a 200 A input current makes the consumption fall to 4 mW per channel.
Very Front End boards
The 216 channels on the six modules of a PCB from a central slab (see Section 1.2) are read out by twelve FLC_PHY3 chips. Two 16-bit calibration ASICs, each having six channels, are also mounted on the PCB. The VFE ASICs are read out in parallel by the off-detector electronics using twelve differential analogue lines. To reduce the crosstalk below 0.1 %, the lines carrying the signals from the modules are spread on six different planes separated by ground planes, giving the 14-layer PCBs. Depending on the type of slabs on which they will be mounted (i.e. central or bottom row), three variants of the PCBs have been assembled: fully equipped with an array of modules (30 used and 12 spares), as shown in Figure 12; and left or right equipped (compared to the orientation in Figure 12) with a row of three modules (15 used and 6 spares for each orientation).
A SCSI connector provides the interface to the off-detector electronics, allowing a full differential link in order to dissociate the digital ground in the readout crate from the detector ground. Each VFE ASIC has a separate channel to the connectors, i.e. there is no further multiplexing on the VFE board. The data transmission is analogue and the analogue-to-digital conversion is done on the off-detector board. A differential buffer is used to convert the single-ended signal provided by the VFE ASIC before transmission. A reference is used for each chip. The digital links are RS-422, allowing a wide common mode range to correct the voltage shift between the VFE PCB, supplied with a negative voltage to optimise the noise, and the off-detector board, supplied with a positive voltage.
2.2 Off-detector electronics
The basic requirements of the off-detector electronics are: to distribute the sample & hold signal required by the VFE electronics within a latency of 180 ns and with an uncertainty of less than 10 ns; to provide the digital sequencing necessary to multiplex the analogue signals from the VFE PCBs; to digitise the signals; and to store the data. The analogue signals have a 13-bit dynamic range, and the electronics is required not to contribute significantly to the analogue noise. Assuming a standard beam test spill structure, the target for the electronics is to run at an event rate of 1 kHz during the beam spill, with an overall average rate of 100 Hz.
The calorimeter readout is based on the “Calice Readout Cards” (CRC) . These are custom-designed, 9U, VME boards derived from the Compact Muon Solenoid tracker Front End Driver readout boards  but with major modifications to the readout and digitisation sections.
Each CRC consists of eight front-end (FE) sections feeding into a single back-end (BE) which provides the interface to VME. The whole board is clocked from an on-board 40 MHz oscillator.
Each FE section can control one full or two half VFE PCBs, totalling 12 VFE readout ASICs, each with 18 multiplexed channels, and hence a total of 216 channels. The FE section consists of a pair of 68-pin mini-SCSI connectors, twelve 16-bit ADCs (one for each readout ASIC) and a Xilinx Virtex-II FPGA. Mini-SCSI cables of 10 m length are used to connect the FEs directly to the VFE PCBs. The digital signals on the mini-SCSI connector are all LVDS and are tracked directly to the FPGA. All VFE ASIC control and clocking signals are generated in the FE FPGA, including the time-critical sample & hold signal edge. The FPGA derives a 160 MHz clock from the 40 MHz board clock, allowing signal timing to 6.25 ns. The FE section also contains two 16-bit DACs for calibration purposes. These can be internally fed back into the ADCs directly, or can be sent onto the mini-SCSI connector to allow calibration of the VFE ASIC. The total data volume within each FE per event for 18 multiplex samples is 512 bytes, including an eight-byte header.
The BE section consists of a Xilinx Virtex-II FPGA controlling an 8 MByte memory. It distributes configuration data to each FE section and gathers the digitised event data from each before storing it in the memory for subsequent readout.
Each CRC is capable of reading out 1728 channels. The data volume per event from these channels is 4 kBytes, allowing 2000 events to be stored in the memory before readout is required. Six CRCs are required for the full ECAL readout of 9720 channels and these are housed in a single VME crate. The VME interface used is the SBS620 VMEbus-PCI bridge .
Some systems other than the CRC VME readout are also integrated into the online system. Tracking (see Section 3) is done using commercial VME TDC units which are installed in spare slots of the CRC crates. Slow data control and readout is implemented via sockets to independent slow control systems. All slow data are written into the data files to ensure the raw data are self-contained.
Trigger and timing
A specific VME slot near the centre of the crate is chosen as the trigger control and distribution CRC and a custom backplane is used to take triggers from this central location to the other CRCs in the crate. The backplane is a simple point-to-point PCB, press-fit to the J0 connectors. The trigger distribution and control is generated in the BE FPGA of the trigger slot CRC and fanned out to the other CRCs. A second fanout on the CRC allows a duplicate set of trigger signals to be taken via a cable to an identical backplane in a second crate, for readout of more than one calorimeter.
The trigger input signals are LVDS and are fed into the J2 connector. The trigger logic is performed within the BE FPGA, allowing significant complexity in the trigger condition to be set via software. This also controls the trigger busy signal, preventing further triggers until the digitisation of the VFE analogue data has been completed.
The trigger rising edge provides the system synchronisation signal and all timings, including those for the time-critical sample & hold, are derived from this edge. To ensure complete events can be built from the same trigger, independent trigger counters are implemented in each of the FE and BE FPGAs, and are read periodically, both during and at the end of each beam spill. If any discrepancy between the counters is observed, all data from the spill following the last valid counter readout are discarded offline.
All trigger inputs, as well as several other input signals, are recorded in a trigger history buffer. This consists of 32 bits, one for each signal, sampled on the 40 MHz clock, recording their state for 256 samples around the trigger time. This allows the detailed time structure of the trigger logic to be observed as well as the readout of several other beam line elements such as veto scintillator counters and a Čerenkov detector.
The complete system performed well in the beam test environment. The sample & hold is distributed on the derived 160 MHz clock within a minimum of 160 ns, allowing the rest of the latency of 180 ns to be implemented as a software-specifiable delay in the FE FPGA. The jitter on this is dominated by rounding to the 6.25 ns clock period. The 16-bit ADCs allow both positive and negative signals although only the upper half is used for the ECAL readout. This still allows them to meet the 13-bit dynamic range requirement, with the two extra bits covering any differential non-linearities or other biases in the ADCs. The CRC noise when the ECAL is disconnected is very low, with an average of 1.4 ADC counts, compared to around 5.9 ADC counts from the ECAL VFE electronics (see Section 4.2.2). The trigger counter synchronisation is very reliable, with a rate of less than one trigger missed on any CRC per million events, resulting in an average event loss of less than one per thousand.
Two significant problems were identified. Firstly, insertion and removal of the cables from the mini-SCSI connectors resulted in breaks in the solder joints, in nearby traces, and in solder connections to nearby FE components, most of which have been fixed by hand. Secondly, there were also problems with the reliability of some of the PCB layer interconnects, and several wires have been added to bypass vias which developed high resistivity. Overall, the system had errors on 3 out of 112 FE sections, none of which were used for data taking.
The online software must support the electronics requirements of 1 kHz instantaneous and 100 Hz average event rates. The maximum event size to be handled is 64 kBytes, allowing for readout of two calorimeters and other beam line equipment. The system is also required to be flexible, so as to handle different beam lines and spill structures.
The code is written in C++ and is specific to Linux, being POSIX compliant as much as possible. No database is used in the online system; all configuration of the hardware is stored in the run data files so that any run can be fully characterised from the data file itself.
The full system achieves a readout rate of 120 Hz when not limited by the beam intensity or spill structure. The average rate during higher intensity spills is found to be around 90 Hz. The trigger rate during spills does not reach 1 kHz but is limited to around 600 Hz. This is mainly determined by the fraction of events for which the trigger counters are read out. These are read with a high frequency to be conservative in checking for synchronisation errors; a lower fraction would allow the specified trigger rate of 1 kHz to be achieved.
The system has recorded up to 10 million events per day and has run efficiently for several beam periods totalling nearly three months. Including 2007 data, around 300 million beam events have been taken, amounting to around 30 TBytes of data.
3 Beam tests
Large scale beam tests are conducted in order to demonstrate the principle of a highly granular Si-W electromagnetic calorimeter. Data analyses are ongoing which will quantify the energy and spatial resolutions, and validate the existing models of electromagnetic and hadronic showers, e.g. the various GEANT4  models. The studies in this article focus on the basic hardware performance when the device is exposed to high energy particles.
3.1 Beam lines at DESY and CERN in 2006
In May 2006, the ECAL prototype was tested with electron beams at DESY, equipped only with 24 layers of central slabs (see Section 1.2). A sketch of the beam test setup is shown in Figure 13. The beam trigger is defined by the coincidence signal of two of the three scintillator counters, referred to as Sc1, Sc2 and Sc3 in Figure 13. The size of the beam can also be defined by two scintillator counters, mounted in a cross shape (Fc1 and Fc2 in Figure 13). Four drift chambers (DC1, DC2, DC3 and DC4) are used to monitor the beam and reconstruct tracks.
In August and October 2006, the ECAL was tested at the H6 area at CERN, in combination with an analogue HCAL prototype  and a Tail Catcher and Muon Tracker prototype , using electron and pion beams. The 30 layers of the ECAL prototype were equipped with central slabs. Sketches of the beam line for both periods are presented in Figure 14. In August, the distance between ECAL and HCAL was large enough to allow the ECAL to be rotated. In October however, the accent was put on minimising this distance so as to use the ECAL as a tracker for pion events. The beam trigger is defined by the coincidence signal of two of the three scintillator counters (Sc2, Sc3 and Sc4 in the August setup, Sc1, Sc3 and Sc4 in the October setup). When it was not used in the trigger, the largest scintillator (Sc3 in August, Sc4 in October) was still read out and so could be used as a beam halo veto offline, using a lack of coincidence between the and cm scintillators. Three delay wire chambers  (DC1, DC2, DC3 in Figure 14) are used to monitor the beam and reconstruct tracks. A Čerenkov detector is used to separate electrons from pions. Muons are identified by two scintillators (Mc1, Mc2) placed behind the HCAL prototype.
3.2 Summary of the data collected
Various scans were performed in order to characterise the prototype. The energy of the electron beams was varied from 1 to 6 at DESY, and from 6 to 50 at CERN, to study linearity and resolution. The beam was positioned near the centre, edge and corner of the wafers to study the uniformity of the wafers and the impact of the passive areas. Events with positrons were also taken from 6 to 50 . The ECAL prototype was rotated by 10, 20, 30 and 45 with respect to the beam direction to study the effects of angular incidence on the linearity and resolution. Finally, and beams were taken with energies from 6 to 80 .
Over 22 million events were collected with electron beams, as detailed in Table 3, and 25 million events with pion beams. In addition, more than 57 million muon events were collected for calibration purposes (see Section 5). An event display of an electron event at 30 is shown in Figure 15.
|Location||DESY (kEvt)||Location||CERN (kEvt)|
4 Pedestal, noise, and crosstalk around module edge
A data-taking run consists of 500 pedestal events, 500 events with charge injection via the calibration chips, and between 10,000 and 40,000 beam data events, after which the sequence repeats. The pedestal and calibration events are taken with a random trigger occurring outside the beam spill period. In addition, pedestal events are taken during the beam spill (every 25 beam events on average), to check the influence of the beam on the pedestals. The determination of the pedestals and noise for the individual channels is described in the following sections. In these sections, the conversion from ADC counts to MIP equivalent units uses the factor 46 ADC counts per MIP (see Section 5).
4.1 Pedestal subtraction procedure
For a given channel, the pedestal is defined by the mean value of the signal recorded with no beam, i.e. coming from electronics, and the noise by the corresponding standard deviation. Instabilities occurring in the time between two sets of pedestal events need to be considered and accounted for in the pedestal subtraction procedure described here. Correlations in the noise also need to be checked, and accounted for if induced by pedestal drifts, and will be described in Section 4.1.2. Once the pedestal subtraction procedure is trusted, the uniformity, the stability in time of any remaining offsets, and the noise in beam-induced events all need to be measured. The results are presented in Section 4.2.
VFE PCB-wise correlated pedestal shifts
The pedestals of all the channels of one VFE PCB are shown, as a function of time, in Figure 16. In this figure, a clear shift in the raw ADC values can be seen between two sets of pedestal events (identified by the blank columns at 680 s and 1030 s). This unexpected effect of pedestal shifts of up to 100 ADC counts (equivalent to approximately two MIPS) for all the channels of a VFE PCB is observed frequently in beam data events. The origin of these shifts has been traced to the non-isolation of the VFE PCB power supply lines, which results in changes to the working point of the output signal lines. This will be corrected in the next PCB design.
In a first iteration, pedestal and noise values are obtained by calculating the mean and standard deviation of the ADC count distribution per channel in the 500 pedestal events taken at the start of each sequence. Averages calculated from a set of pedestal events are then simply subtracted from the ADC values recorded in the following set of beam events. The shift in the pedestals will affect the apparent noise, as the reference value is fixed by the previous set of pedestal events: the noise will appear to be artificially large, and 100 % correlated within the PCB if the shift is common to all channels. The left-hand plot of Figure 17 shows the correlation coefficients (averaged over one run) between the apparent noise on the 216 channels of a particular VFE PCB, calculated after this simple pedestal subtraction. Channels are ordered by wafers, so 36 consecutive channels belong to the same wafer in the readout channel index displayed. The apparent noise is highly correlated between all channels, indicative of a common shift in the pedestal values.
It is therefore important to correct the pedestals on an event-by-event basis, by detecting and correcting shifts compared with the previous estimate. Hence, a second iteration on the pedestal value is performed. A sample of channels is defined on each VFE PCB by selecting modules without signal hits. For this purpose, it is assumed that a signal was recorded if the difference between the minimum and the maximum of the pedestal-subtracted ADC values of the 36 channels in a module exceeds 3000 ADC counts. For this sample, a first estimate of the mean pedestal value is taken to be the average of the minimum channel value per chip, plus five times the noise. The root-mean-square (RMS) deviation from this mean is calculated using only the channels having ADC values smaller than the mean. This is to avoid being biased by the signal. For each VFE PCB, a single offset is then estimated by iterating on the mean value (and hence the channels taken into account in the calculation of the RMS) until the RMS is compatible with the mean noise of the PCB, with a maximum of 20 iterations. The right-hand plot of Figure 17 shows the noise correlation coefficients after applying this procedure. The mean correlation is reduced to , indicating that the procedure has successfully corrected for the shifts.
Correlated noise and signal-induced pedestal shift
Some modules recording a high signal are subject to a different effect, namely a signal-induced pedestal shift (SIPS), resulting in apparent high noise correlations for all 36 channels on a module. This can be seen in Figure 18, left, for the VFE PCB situated in the tenth layer, for the same run as in Figure 17, after applying the corrections described in Section 4.1.1.
However, the SIPS effects are not systematic, in that they do not affect all PCBs, and, for those affected, the effect is not always present. What is inducing this phenomenon is not yet understood, but a possible explanation could be that there is an intermittent bad contact between the
aluminum foil and the module. A common serial resistance to all pads of a few Ohms would produce the same effect. A strong correlation between the negative pedestal shift and the amplitude of the signal is observed, as shown in Figure 19.
The SIPS are corrected on an event-by-event basis. Inspired by the corrections described in Section 4.1.1, averages are considered per module, rather than per PCB, discarding hits with signal, and iterating on the mean, standard deviation, and channels taken into account in the calculations. The result after corrections can be seen in Figure 18, right. The corrections perform well, the average correlation over the whole PCB being reduced by a factor of three, and the standard deviation of the correlation coefficients by one order of magnitude.
4.2 Uniformity and stability of the residual pedestals and noise
For more systematic studies of uniformity and stability in time and temperature, the residual pedestal and noise will from now on be defined by the mean and standard deviation of the Gaussian fit of the noise component of the spectrum in beam induced events (see first peak in Figure 9), after pedestal subtraction and all corrections as described above. Noise and residual pedestal values are verified to be stable within a run. The full statistics of each run is hence used to perform the fit, and the run dependence studied.
The uncertainties on the residual pedestal and noise in the following sections arise from the uncertainties from the fit on each parameter. The noise peak is fitted iteratively in the range , to avoid being biased by the signal. By varying the fit range, an additional systematic uncertainty of is found and added in quadrature to the uncertainty on the noise.
Uniformity and stability of the residual pedestals
Figure 20 shows the residual pedestals for a particular run taken with electrons, as a function of the pad index. The pad index is defined as , where is the layer index, () is the module row (column) index, and () is the pad row (column) index. Results are not shown for the nine channels (out of 6471 active channels, see Section 5.2) where the Gaussian fit to the noise peak did not converge. The average residual pedestal over all channels is ADC counts for this particular run, with a standard deviation of ADC counts. A larger scattering can be seen around the shower maximum, indicating a possible remaining influence of the SIPS described in Section 4.1.2. A periodic structure may be noted, whose period is 216 channels, i.e. PCB-related, and reflects the differences in length of the electronics connection from each pad to its readout chip.
Figure 21 shows the mean and standard deviation of the residual pedestals averaged over all channels, for other runs taken in October 2006, as a function of the run number. Very similar results are obtained for the August runs. Pion and muon runs have systematically less spread between channels than electron runs, and a mean value closer to zero, indicating again a possible remaining influence of the SIPS on the pedestals.
On average over all channels, the pedestals in electron runs are subtracted with a remaining positive offset of ADC counts ( % of a MIP). The residual standard deviation channel-to-channel is however ADC counts ( % of a MIP), which justifies investigating the channel dependence in the following.
The residual pedestal per channel and per run is found to not have any clear dependence on time or temperature, with no observable day/night variations, nor any dependence on the beam energy of the run. In order to study more systematically the time dependence for each channel, the mean and standard deviation over all runs weighted by the error per run are considered per channel, and displayed in Figure 22 for all channels, for CERN electron runs. The mean pedestal offset is smaller than % of a MIP with a standard deviation channel-to-channel of % of a MIP. The residual offset run-to-run is of the order of % of a MIP, with a standard deviation channel-to-channel of % of a MIP.
The effect of a systematic pedestal offset on the energy scale is additive, and so the mean offset scales with the number of hits recorded. To give an estimate of the size of the effect, a 1 (45 ) electron will produce around 250 MIPs (6000 MIPs). If these are distributed over 100 (400) hits, the impact of the remaining pedestal offset will be around 0.2 MIP (0.8 MIP), i.e. 1 MeV (3 MeV), which can be neglected.
Uniformity and stability of the noise
Figure 23 shows the noise per channel as a function of the same pad index as used in Figure 20, and for the same electron run. Some channels have an intrinsically high noise, often in (anti)correlation with a neighbouring channel. On average over all channels, the noise with this method is found to be ADC counts with a standard deviation of ADC counts, for this particular run.
Figure 24 shows the mean and standard deviation of the noise averaged over all channels, for other runs taken in October 2006, as a function of the run number. Very similar results are obtained for the August runs. On average over all channels, the noise is ADC counts ( % of a MIP), with a run-to-run dependence smaller than 1 % of the mean noise, and a channel-to-channel dependence of about 9 % of the mean noise, which justifies considering the channel dependence in the following.
As for the residual pedestal, no clear correlations are seen as a function of time, temperature (day/night variations), or beam energy. In order to study more systematically the time dependence for each channel, the mean noise value over all runs weighted by the error per run is considered per channel, and displayed for all channels in Figure 25, left, for CERN electron runs. The mean noise is % of a MIP, with a spread channel-to-channel of % of a MIP. The standard deviation in time is smaller than 0.3 % of a MIP on average, with a spread channel-to-channel of less than 0.2 % of a MIP. The standard deviation per channel normalised by the corresponding noise per channel is represented in Figure 25, right. On average over both periods, the relative spread run-to-run is % with a spread between channels of %. With about 20 % of the channels having run-to-run variations above 3 %, a run-by-run approach to measure the noise is required.
The impact of the noise on the energy scales with the square root of the number of hits: for 100 (400) hits in the case of a 1 (45 ) incident electron, the noise contributes less than 0.5 %/ to the total energy resolution.
Pedestals are subtracted with a remaining offset smaller than 0.2 % of a MIP, but with channel-to-channel variations of % of a MIP, and run-to-run variations of % of a MIP. The impact on the energy scale depends on the number of hits recorded, in MIP units, which can be neglected.
The noise per channel is % of a MIP on average for all channels, with variations in time averaged over all channels of %. About 20 % (6 %) of the channels have time variations greater than 3 % (5 %), requiring a run-by-run approach to extract the noise measurements. The impact on the energy resolution also depends on the number of hits recorded, in MIP units. Since (400) for 1 (45 ), this is therefore negligible.
4.3 Crosstalk around the module edge
In some events (as shown in the event display in Figure 27), when a large quantity of energy is deposited in the proximity of the guard rings, a signal of almost constant amplitude appears on all peripheral pads, except for the four pads of the corners where this amplitude is twice as large. These “square events” are due to capacitive coupling which exists between the guard rings and the peripheral pads. From the measurements, about 1% of the charge deposited in the guard ring is propagated into each border pixel (and twice as much into the corner pixels), which is compatible with the simulation of a simple electrical model shown in Figure 27.
Following the idea of a capacitive coupling between guard rings and bordering pads, a straightforward option is to cut the guard rings into small segments. This layout technique should result in the coupling capacitance being in series, thus dividing the coupling effects. Following preliminary simulation studies, the segmented topology design option for the guard rings is shown to lower the crosstalk effects by a factor ranging from 3 to 30 according to the actual distances of the elements of the design. The simulation work is ongoing and other design options are being evaluated. Measurements on real modules will complete this work.
The criterion for identifying square events in the beam test data is based on two characteristics of the border hits involved in square patterns. Firstly, a border hit is considered as isolated if its neighbours are only other border hits. Secondly, two border hits are linked if there is a path between them along the border without any gap. In a module, a square pattern is found each time the number of border hits which are isolated and linked is greater than nine, established with the help of Monte Carlo data. The Monte Carlo does not include the simulation of the crosstalk.
The probability for a module to display a square pattern according to the above criterion is shown in Figure 28 for both August and October periods of data taking at CERN. The error bars displayed in Figure 28 contain the systematic uncertainty associated with varying the selection cut between eight and ten linked border hits, in quadrature with the statistical uncertainty. It is seen that, as expected for a crosstalk effect with a detection threshold, the rate increases with the energy of the electron beam, but remains stable in time for a given energy and beam profile. For both periods, the beam was pointing towards a guard ring, but its geometrical spread was larger in August. This leads to a higher rate of square patterns in October, since the rate also increases when the particle becomes closer to the guard ring. Given this geometrical consideration, it is not reliable to quote a rate of square events independent of a particular beam setting.
5 Calibration of the detector
Muons are used to calibrate the detector in terms of MIPs. After checking the stability in time of the noise component in muon events, the conversion factor from ADC counts to MIP equivalent energies needs to be extracted per channel, using a large sample of muon data to reduce the statistical fluctuations. The uniformity and the stability in time of the calibration constants need to be checked, as well as the possible sources of systematic uncertainties that will influence any energy measurement. The method and results are detailed in the following sections.
5.1 Extraction of the calibration constants per channel
The calibration of the ECAL prototype was performed using 74 beam halo muon runs ( events each), recorded during October 2006. A further 18 runs were recorded in August 2006. Another experiment upstream helped to provide a wide spread of the muon beam over the whole surface of the prototype. Events were triggered with a 1 m scintillator counter. An event display of a muon event is shown in Figure 29.
The first stage in the analysis of muon events is substract the pedestals from the raw data, as described in Section 4.1. The pedestal subtraction is performed with an accuracy of 0.1 ADC counts (0.2 % of a MIP) on average for all channels, taken as a systematic uncertainty for the calibration constants.
The calibration constants are calculated for each channel using the hit energy distribution in identified beam halo muon events. The event sample is selected by requiring the presence of a track which is consistent with being a MIP, based on two criteria. Firstly, the total number of reconstructed hits in the 30 layers of the ECAL must be between 15 and 40. Secondly, the distance between two hits in consecutive layers must be less than 2 cm. As the residual pedestals are shown to be negligible compared to the estimated MIP signal (0.2 % of a MIP), they are not subtracted from the measured value of the MIP peak position. Furthermore, with a mean noise of % of a MIP, the noise tail is neglected and only the MIP contribution in the hit energy distribution is fitted.
For each channel, the distribution of hit energies (in ADC counts) is made from the sample of selected muons. Since the muon spread is not totally uniform over the whole surface, the number of hits in the distributions varies from a few thousand in the border regions to up to 14,000 in the central part. The hit energy distribution is fitted to a convolution of a Landau distribution and a Gaussian. An example fit is shown in Figure 30. The most probable value of the Landau function gives the calibration constant, while the standard deviation of the Gaussian gives an estimate of the noise value for each channel. The fitting range has been limited between 25 and 78.5 ADC counts.
The statistical uncertainty on the fitted value of , calculated by TMinuit , is ADC counts on average for all channels, with a spread between channels of ADC counts. In addition, as stated above, the pedestal subtraction introduces an additional uncertainty of ADC counts. If the entire ADC range is fitted rather than the range 25-78.5 ADC counts, the difference is found to be ADC counts on average over all channels, with a spread between channels of ADC counts. The latter value is considered as a systematic uncertainty on the calibration constants . The total statistical uncertainty on each calibration constant is hence about 0.24 ADC counts (0.5 % of a MIP), and the total systematic uncertainty 0.18 ADC counts (0.4 % of a MIP).
For 6403 out of the 6480 channels of the prototype, the MIP calibration is obtained using the above procedure. One entire module (36 channels) shows no signal above 25 ADC counts, as a result of the silicon not being fully depleted. The ratio between the mean MIP signals of this module and a randomly chosen neighbour is estimated to be 0.517, allowing a relative calibration of its channels. Nine channels have readout issues, and are declared dead. For the remaining 32 channels, the fit described above fails due to anomalously high levels of noise. 18 of these are recovered by fitting with the sum of a Gaussian and the previously used function. The other 14 are calibrated using neighbouring pads. The calibration constants are found to have slight variations chip-to-chip. The spread between chips is found to be ADC counts (1.7 % of a MIP) on average, hence this value is taken as systematic uncertainty for the 50 channels calibrated using neighbouring pads.
Uniformity across the detector
The calibration constants for all channels are shown in Figure 31 as a function of the pad index. Three main categories of channels can be identified in Figure 31, linked to the gluing date and the module origin. The first category (in black) at around 44 ADC counts contains layers 0 to 13 and layer 20 and corresponds to wafers produced by the Institute of Nuclear Physics, Moscow State University , glued at the end of 2004. The second category (in blue) at around 46 ADC counts contains layers 14 to 19, layer 21 and layer 24, and corresponds to wafers from the same manufacturer glued between October 2005 and May 2006. The third category (in green) at around 47.5 ADC counts contains layers 22 and 23, and layers 25 to 29, and corresponds to wafers produced by the second manufacturer (ON Semiconductor Czech Republic , with the Institute of Physics, Academy of Sciences of the Czech Republic, Prague), glued in 2006.
Stability in time
To check the stability in time of the calibration constants, the values obtained with the above sample of beam halo muons recorded in October 2006 are compared with the test bench measurements, taken before the mounting of the slabs (see Section 1.3.2). They are also compared with a sample of beam halo muons recorded in August 2006 in similar conditions.
Test bench measurements were made between 2004 and 2006 (see Section 1.3.2), giving an average per chip (i.e. per 18 channels), with an uncertainty of 5 % (2.2 ADC counts on average), and with a different DAQ. These are plotted against the average per chip calculated for the October 2006 muon runs in Figure 33. A clear correlation can be seen for all channels with the exception of one chip that was measured at a high gain with the cosmics test bench, but has a more standard value with the muon measurement. This chip would appear at G ADC counts and G ADC counts in Figure 33. The correlation factor between the two datasets is found to be 75.8 %, discarding the outlier chips. None of the chips has deteriorated, confirming a stable and reliable behaviour of the chips with time.
The August sample results are plotted against the October sample results in Figure 33. A correlation coefficient of 93.2 % is found between both datasets. The difference between October and August values is plotted against the pad index in Figure 34. The mean value of the difference for all channels is found to be ADC counts with a spread of ADC counts.
The systematic shift of about 1.5 % of a MIP shown in Figure 34 is not yet understood, and is being investigated. If it is due to some timing offset in the triggers, such that the sample & hold is offset with respect to the shaper peak, an additional correlated systematic uncertainty of about 1.5 % of a MIP would have to be considered on the energy scale, as the trigger used to record electron or pion beams could have different timing settings again. Otherwise, if the shift is, for example, due to a different operation voltage of the VFE PCBs, then different calibration constants are required for the different periods of data taking.
For 99.09 % of the channels, the calibration constants are obtained from a convergent fit with a statistical uncertainty of 0.5 % of a MIP and a systematic uncertainty of 0.4 % of a MIP. For 0.77 % of the channels, it is necessary to copy the calibration constant from a neighbouring pad. This results in a higher systematic uncertainty of 1.7 % of a MIP, coming from the standard deviation of the calibration constants obtained from a convergent fit per chip. The remaining 0.14 % of channels are declared dead.
The mean and standard deviation of the calibration constants for all channels are summarised in Table 4, for the three measurement in time that have been made. The correlation coefficient between the October and the August (cosmics setup) samples is found to be 93.2 % (75.8 %) indicating a reasonable stability with time. The systematic shift of 1.5 % of a MIP found between the August and October samples however needs to be understood. Studies are ongoing by comparing to additional samples taken in 2007 at CERN.
|Cosmics 2004-2006||August 2006||October 2006|
|Mean (ADC counts)|
|RMS/Mean (ADC counts)|
The CALICE ECAL Si-W prototype is a large scale prototype with nearly 10,000 channels when completed, of which 6,480 were studied in this document. The chosen technology, specifically high granularity together with a compact structure, is compatible with the physics goals of an ILC, through the use of a particle flow approach for the reconstruction of events. Since a final ILC detector could have a coverage of around 3,000 m of silicon, the wafer price must be kept low and this has been a primary aim of the sensor design. Wafers have been produced, and continue to be produced, by several manufacturers, both to keep the price down and to test several fabrication technologies.
As expected when building and testing new prototypes, issues have been encountered. The mechanical design and DAQ have proven themselves very reliable. The affected parts in the design and test procedure were mainly the wafer production and the module design, and electronics issues with power supply lines and grounding.
The first problem encountered affected the module, once glued on the VFE PCB, with incompatibilities observed between the chemical passivation used by the manufacturers and the gluing process. This was solved with the producer, and has now proven reliable over period of years.
When the prototype was first put in beam, further issues were discovered at the module level. The first one concerns a capacitive coupling between the guard ring and the peripheral pads, discovered through the observation of so-called “square events”. This is being investigated and modelled with simulation, in order to reduce the crosstalk in the next design. Methods are also being developed to identify these events reliably in the beam test data. The second issue, observed through the sudden shift of all the pedestal signals of a module, proportional to the amplitude of the signal recorded in the module (and hence to the energy of the incoming particle), is not yet understood. An intermittent bad contact between the Aluminium foil providing the ground and the module could explain such an effect but is hard to diagnose. An improved isolation and grounding system is being investigated.
The last issue encountered, observed through the sudden shift of all the pedestal signals of a VFE PCB by the same amount, has since been attributed to the non-isolation of the VFE PCB power supply lines. No working fix has been provided yet but the design is being corrected for the next prototype.
Large datasets have been acquired in beam tests at both DESY and CERN. Pedestals were found with a remaining offset smaller than 0.2 % of a MIP, with channel-to-channel variations of % of a MIP, and run-to-run variations of % of a MIP in electron and pion runs. However, in the muon runs used to calibrate the response of each channel, the channel and time variations are smaller than 0.4 % of a MIP, ensuring a negligible impact on the energy scale.
The noise is around 13 % of a MIP for all channels, with 20 % of the channels having time variation greater than 3 %. The impact on the energy resolution will be in MIP units, with the number of hits recorded above threshold.
Overall, the calibration constants are found with an error of 0.5 % of a MIP. A systematic shift of less than 2 % of a MIP is found between values measured in the summer (August 2006) and in autumn (October 2006), indicating reasonable stability. In addition, the comparison with cosmics test bench measurements taken several years before the beam tests shows a good correlation between the two sets of measurements, indicating a stable and reliable behaviour of the wafers over periods of years.
We would like to thank the technicians and the engineers who contributed to the design and construction of the prototypes, including U.Cornett, G.Falley, K.Gadow, P.Göttlicher, S.Karstensen and P.Smirnov. We also gratefully acknowledge the DESY and CERN managements for their support and hospitality, and their accelerator staff for the reliable and efficient beam operation. We would like to thank the HEP group of the University of Tsukuba for the loan of drift chambers for the DESY test beam. The authors would like to thank the RIMST (Zelenograd) group for their help and sensors manufacturing. This work was supported by the Bundesministerium für Bildung und Forschung, Germany; by the Helmholtz-Nachwuchsgruppen grant VH-NG-206; by the BMBF, grant no. 05HS6VH1; by the Alexander von Humboldt Foundation (Research Award IV, RUS1066839 GSA); by joint Helmholtz Foundation and RFBR grant HRJRG-002, Russian Agency for Atomic Energy, ISTC grant 3090; by Russian Grants SS-1329.2008.2 and RFBR0402/17307a and by the Russian Ministry of Education and Science; by CRI(MST) of MOST/KOSEF in Korea; by the US Department of Energy and the US National Science Foundation; by the Ministry of Education, Youth and Sports of the Czech Republic under the projects AV0 Z3407391, AV0 Z10100502, LC527 and by the Grant Agency of the Czech Republic under the project 202/05/0653; and by the Science and Technology Facilities Council, UK.
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