An Analytical Approach
for Memristive Nanoarchitectures
Abstract
As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique  characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneakpath currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and hence provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.
I Introduction
Emerging memory technologies based on new materials have been widely accepted as alternatives to the current CMOS technology. These technologies are mainly classified in three subclasses: Magnetoresistive Random Access Memory (MRAM), Phase Change RAM (PCRAM), and Resistive Memory (ReRAM) [1]. Memory applications motivate the need for an evaluation of these technologies in terms of READ and WRITE bandwidth, latency, and energy dissipation. The International Technology Roadmap for Semiconductors [1], highlights that the performance characteristics of these emerging technologies are rather promising when compared with the curent large memory arrays based on Static RAM (SRAM) constructs, particularly for large memory capacities. This suggests that emerging technologies, except PCRAM, will overtake advanced conventional Complementary Metal Oxide Semiconductor (CMOS) technology. We define a figure of merit as for comparing these technologies—with greater emphasis on the access time—the parameters represent READ and WRITE energy (, ), READ and WRITE latencies (, ), and the number of refresh cycles (). This figure of merit indicates around , , and improvement for ReRAMs, MRAMs, and PCRAMs, respectively, over SRAMs for large memory capacities ( GB) [1]. The READ and WRITE access times of MRAMs show around more and less processing time than ReRAMs. ReRAMs introduce smaller cell size, /bit, where is the lithographic feature size, see Fig. 1(c), with comparable endurance in comparison with the other memory technologies. Although a number of strategies that utilize diode and/or transistor crosspoint devices are proposed, their fabrication is relatively more complex than a ReRAM crossbar [2].
The mathematical foundation of the memristor^{1}^{1}1The term memristor is a portmanteau of memory and resistor., as the fourth fundamental passive element, has been expounded by Leon Chua [3] and later extended to a more broad class of memristors, known as memristive devices and systems [4]. This broad classification today includes all resistance switching memory devices such as ReRAMs [5]. Realization of a solidstate memristor in 2008 [6] has generated realization of both large memory arrays as well as new opportunities in the neuromorphic engineering domain [7, 8, 9, 10, 11, 12, 13].
Although the memristor has introduced new possibilities for memory applications within the simple and relatively low cost crossbar array architectures, the inherent interfering current paths between neighboring cells of an addressed cell impose limitations on the scalability, a necessary condition for large memory arrays [14].
The imposed limitation was addressed by Linn et al. [14] through adaptation of two series memristive elements connected with opposing polarities. This structure is referred to as Complementary Resistive Switch (CRS) as shown in Fig. 2. The unique aspect of this device is in using a series of high resistance states (HRS), , and low resistance states (LRS), , to introduce logic “0” and logic “1”. As an example, a LRS/HRS combination represents “1” and a HRS/LRS state represents “0”. Using this approach, the net resistance of the device is always around the HRS, , which helps in reducing sneakpath currents and at the same time main path currents. The advantage of using a CRS as a fundamental element originates from its excellent READ voltage margin, even with small HRS to LRS ratios. Moreover, it facilitates a comparable WRITE margin [15]. There is also a lack of SPICE model verification for CRS devices and a statistical analysis considering the mentioned operational uncertainties. Here, we address these issues using a VerilogA implementation for memristor dynamics within a memristor macromodel for SPICE simulation.
Contributions in this paper can be categorized in five parts:

CRS device modeling and verification using available functionality information from [14].

Comprehensive mathematical framework for a memristive array for assisting designers to identify the impacts of stored memory pattern, parasitic resistances, and sneakpath currents on the array performance. In addition, we develop a system of linear equations to extract the voltage pattern across an array regardless of the READ or WRITE scheme. This mathematical framework can be used for different emerging memory devices.

Characterization of a comprehensive framework for a CRS array and identifying an optimal value for load resistors in a CRS array.

Highlighting the importance of the WRITE scheme and array size in the total power dissipation through an analysis of the number of halfselected cells in array for memristivebased and CRSbased arrays.

It is also shown that the existence of a long tail distribution in LRS resistance, after several thousand operation cycles, process variation, temperature effects, and uncertainties related to the nanowire parasitic resistances have significant impact on a memristor crosspoint array than a CRS array.
Along with addressing the parasitic current path issue, the importance of parasitic resistors also increases as reduces. In a practical memory design, the line resistance of a nanowire can be calculated with , where is the number of cells in the line and is the resistivity of metal, which is a function of [16]. Therefore, a mathematical model is developed to consider the nanowire parasitic resistances in a matrix based analysis of crosspoint arrays.
In this paper, the preliminaries of memristor technology and modeling approach based on a fabricated MetalInsulatorMetal (MIM) structure is presented in Section II. Then a practical model of the CRS device is developed and created in SPICE as a macromodel. This is described in Section III. Section IV shows the analytical crosspoint model and mathematical model as well as simulation results and discussions.
Ii Memristors
Memristive device modeling is a necessary step for CRS device modeling. Therefore, we first present the memristive element characteristics, which can be defined using two equations,
(1)  
where is a physical variable indicating the internal memristor state that in theory is such that , where is the thickness of transient material oxide (TMO) thinfilm. The parameters and represent current and applied voltage, respectively. The second expression of Eq. (1) defines velocity of this movement. Considering an ionic conduction mechanism, this part can be redefined as an ionic drift velocity. The function captures the highly nonlinear characteristics of the memristor as function of the applied voltage [17, 18, 19]. The  curve relationship, as in Eq. (1), has already proposed by several groups [20, 21, 22, 23], however, an accurate reproduction of the characteristics in simulation is an area of intense research. An appropriate function seems to be either a double exponential or related forms [19, 22], or a function [18], which defines intrinsic threshold voltages. Here we apply a commonly accepted function to our experimental data. The memristor state variable is identified through time integral of the function and then it is applied to the function. The outcome shows a good agreement between the measured data and the modeled  hysteresis.
To address this modeling problem we use the Mott et al. [24, Chap. 2] model of ionic conduction in terms of the theory of lattice defects that has been already used in several studies in this area [15]. In this case,
(2) 
where is initial velocity, is the potential barrier height, represents the Boltzmann constant, temperature, and applied voltage in eV. The parameter , which is a dimensionless parameter related to the distance between adjunct lattice positions, , and TMO thickness . For approximating the effective electric field in the equation, should be a function of in the way that . Quantities are summarized in Table I.
The relationship between the drift velocity and device thickness, , clearly shows the reason that memristive behavior appears strictly at nano scale dimentions. A detailed comparison between the model and experimental data is given by Heuer et al. [25].
The virgin device needs an electroforming step that acts like a soft breakdown condition and creates a conductive channel through the TMO material (TiO in our case). Then the applied voltage polarity identify the channel orientation [26, 27, 28]. In our case, the forming step is carried out by applying an electric field around MV/cm across TiO. This forming step creates a difference in atomic percentage ratio of oxygen in TiO close to one of the electrodes. The conducting mechanism is then carried out through a channel known as a conducting filament (CF). The conducting filament is highly localized (e.g. for a cylindrical CF, nm) compared to the metalic contact area, , and the filament (ON) resistance is proportional to [29]. This shows that controlling the filament area is very important for controlling the programming current in an array of ReRAM elements. Controlling is possible through a set of operations. It is also reported that the SET threshold smoothly increases as increases, , whereas a significant decrease in was reported [29].
A VerilogA implementation of this model is used as a macromodel in Cadence. The macromodel implements the function as . Our experiments show that a linear  is in agreement with measurement results for an area of m [22]. Further reduction of the device feature size, , is possible. However, issue related to crosstalk and tunneling between neighboring cells should be taken into account [16, 30, 31]. The OFF current can be defined as , where , , , and are fitting parameters. Different  equations for ON and OFF states have been also reported in [32] and [33]. For instance, Inoue et al. [33] reported and . Section IVC includes a discussion on using the nonlinearity of the memristor characteristics for increasing at a given READ operation voltage.
Parameter  Value  Units  Reference 

[18]  
attempts/s  [18]  
eV  [34]  
1500  m/s  calculated  
nm  fabricated  
no units  calculated  
W/(Km)  [35]  
m  fabricated  
nm  [29]  
K/W  calculated 
Fig. 1 illustrates the modeling results for a memristor based on experimental data from a Silver/Titanium dioxide/Indium Thin Oxide (Ag/TiO/TiO/ITO) measurement implementation [22]. This is a novel combination for an ReRAM implementation in using TiO as the TMO material according to Table 1 in [30]. This implementation yields a bipolar cell with nearly successful cycles. Besides asymmetry, recent studies shows that the inherent Joule heating effect is responsible for (RESET) switching mechanism in a way that sufficient heat induces a crystallization of the oxide surrounding the channel [26, 36]. This crystallization time frame is exponentially related to temperature [26]. The exact equation can be extracted from [29]. Therefore, as Joule heating increases in the hysteresis, the CF diameter (hot spot) shrinks and this effect would lead to a reset. We include this effect in our macromodeling approach using a relationship introduced in [37],
(3) 
where K, is the thermal resistance, is Joule dissipation at reset, and is TiO thin film thermal conductivity. According to experimental data, as decreases, RESET current decreases, so the RESET threshold voltage would increase [36].
In order to increase simulation convergence Eq. (2) can be rewritten as,
(4) 
where , , and are lowfield and higher order coefficients. This approach also combines the effects of Joule heating and (on the effective electric field) in coefficients. Note that usually defines a pure memristive behavior, as described in [3].
These properties then raise the following questions, (i) how to address the asymmetric characteristic in WRITE and READ operations, (ii) what is the impact of using more realistic model for crosspoint array evaluation, and (iii) what is the effect of different device level  characteristics on the array performance? Here we are aiming to answer the first two questions using the explained model and the answer to the third question is currently under review by the our research group and will be the topic of another paper. The second question can be answered using a worstcase consideration for . In this case, this paper compares a memristor array with a CRSbased array.
Using the developed model of the memristor that accurately models the nonlinear behavior of the device, we can model the CRS as explained in the following section.
Iii Complementary Resistive Switch
A CRS is a resistive switching device that is built using two memristor devices connected in series with opposite polarities [14]. Fig. 2(c) illustrates the modeling results. The figure’s inset illustrates a CRS based crosspoint array. Each memristor in the figure follows a  curve relationship that is shown in Fig. 1(a). The minimum applied voltage for a switch is around V. Considering the CRS structure as a simple voltage divider, for a LRS/LRS situation^{2}^{2}2This situation is defined as the ON state. This is not a stable state so it does not represent a logic state but plays an important role in the switching, READ, and WRITE processes. minimum V is applied across either of the memristors. Please refer to Table III for the crossbar memory array parameters. CRS’s ON state resistance is , where represents memristor’s LRS and CRS’s high resistance, , where indicates memristor’s HRS (see Table II). Fig. 3 highlights the resistance switching of the CRS device. The initial state is programmed to be slightly below , so there is a difference at the initial curve and the rest of the sweeps. In a memristor device, logic “0” and “1” are represented with and , respectively, whereas a CRS device represents logic “0” and “1” using a combination of low and high resistances which results in overall resistance of () for the both logical values.
A fresh CRS device shows a HRS/HRS resistance for memristors A and B. This combination occurs only once (this is not shown in the figure) [27]. After applying a positive or negative bias, depending on the polarity of memristors, the device switches to either the “0” or “1” state. In Fig. 2(c), red lines are threshold voltages for SET and and for RESET and . In an ideal CRS device, and . Here V and V. A successful READ operation occurs if . For a successful WRITE, . Consequently, every voltage below should not contribute any change in the device state. Possible state transitions are shown in Table II, where shows the next resistance state, illustrates the initial resistance state, and output is a current pulse or spike. In this table, H represents high resistance (either logic states, Logic “” or Logic “1”), and L indicates low resistance.
The simplest analytical model of a CRS can be defined in a relative velocity form, when and the two memristors (A and B) form a voltage divider. Therefore, depending on the combination, the difference between and can be identified.
Output  

H (“1”)  L (ON)  pulse  
H (“1”)  H (“0”)  spike  
H (“0”)  L (ON)  pulse  
H (“0”)  H (“1”)  spike  
L (ON)  H (“0”)  –  
L (ON)  H (“1”)  – 
The first feature that appears from the CRS simulation, and device fabrication [14, 38], is a perfectly symmetric  curve out of an asymmetric memristor  curve. The device is programmed initially at logic “1”, LRS/HRS, (LRS and HRS). An appropriate READ pulse creates a high potential difference across while the voltage difference across is not beyond its memristive threshold. Therefore, switches to LRS and an ON current (pulse) passes through the CRS device. After a resting time, a negative WRITE pulse is applied to restore “1”, which can be defined as refreshing procedure. Fig. 4(b) shows that the settled close to HRS with a logic “1” stored in the device. Then a positive WRITE pulse tends to write logic “0”, which can be defined as programming step. Depending on the switching speed of the memristors, a short term ON state occurs that causes a relatively large current spike (encircled by red dots in Fig. 4(a)). There are other functional characteristics that have to be met. For instance, a HRS/HRS state should not appear in any of the situations that are demonstrated by the presented simulation [15].
The CRS device shows several advantages over a single memristor element for memory applications. This work highlights these advantages for nano crossbar memories.
Iv Crossbar Memory Array
A crossbar structure as shown in Fig. 5(a) is used. This hybrid nano/CMOS implementation is a 3D implementation that the nano domain is stacked on top of the CMOS domain [39]. The crosspoint element could be either a CRS device or a memristor. In order to read any stored bit in , similar to many other reported schemes [40, 2, 41, 42], here we apply to the bitline, wordline is grounded, and all other word and bit lines are floating. A direct benefit of this approach is the pullup resistor () can be implemented in nano domain [41]. The stored state of the device then can be read by measuring voltage that is performed by using CMOS sense amplifiers (SAs). Reading “1” creates a current pulse, and as a consequence, a voltage pulse appears on the middle electrode. Note that the CRS readout mechanism does not rely on sensing the middle electrode (ME) and this electrode is floating. The readout mechanism detects the affect of this current pulse on the bitline’s nanowire capacitor and senses it with the SA array.
The WRITE scheme that is used is the common accessing method in which the bitline is pulled up, the wordline is grounded, and the other lines are all connected to , where is the WRITE voltage. This voltage should be high enough to create sufficient voltage difference across the target cell and at the same time having no unwanted affect on the other cells that mainly see a voltage difference.
Although the WRITE operation in memristors dominates because of its relatively high voltage/current, for CRS device the READ current dominates the current level. Therefore, in our case, the READ operation analysis for energy consumption and performance characteristics is more critical than WRITE operation. Consequently, we discuss the READ and WRITE simulation results here. Table III highlights the crosspoint junction and array parameters.
Parameter  Value  Array  Description 

k  (M)  low resistance state  
k  (C)  low resistance state  
M  (B)  high resistance state  
(M)  resistance ratio  
(B)  input resistance of SA  
(B)  pulldown resistance  
(B)  pullup resistor  
(B)  parasitic resistor  
V  (M)  SET threshold  
V  (M)  RESET threshold  
V  (M)  READ voltage  
V  (M)  WRITE voltage  
V  (C)  SET threshold  
V  (C)  RESET threshold  
V  (C)  read voltage  
V  (C)  write voltage 
Array type: (M) Memristorbased, (C) CRSbased, (B) Applicable for both.
We assumed that bitlines are directly connected to sense amplifiers (SAs) and there is no in between.
It is assumed that these resistors are implemented in nano domain. Transistors in Fig. 5 are used to express a more general form of a hybrid nano/CMOS memory.
Lumped parasitic resistance of an activated pulldown.
To analyze the structure, we need to provide a simplified equivalent circuit for the crossbar structure, as can be seen in Fig. 5(b) and (c). Note that and . Fig. 5(c) illustrates the equivalent circuit considering sneakpath currents for the both memristive and CRSbased array. For the sake of simplicity, two series resistors, and , are evaluated separately.
The resistor value for the memristivebased and CRSbased circuit can be written as,
(5)  
(6)  
(7)  
(8) 
where represents the array’s stored pattern in three different groups as seen in Fig. 5(a). For the worst case READ or WRITE in a memristive array and for a CRS array logic “1” or logic “0”, whereas logic “1”. Although a worst case cell selection is considered here, due to the harmonic series behavior of the overall parallel parasitic resistance, increasing and/or decreasing the array size, , results in better agreement with the analytical approximation for and . These equations then can be used for evaluating the impact of parasitic current paths and parasitic nanowire resistors on the array performance.
The worst case pattern is assumed to be applied when logic “1” for either memristive or CRS array. In this case, we have the most significant voltage drop because of the both parasitic paths and elements. Therefore, a pattern of either logic “0” or “1” for all the elements except those on wordline () is assumed, which is roughly equivalent to a HRS resistance for a CRS device, . A close look at Fig. 4(a) and (c) shows if the stored logic in all the CRS devices along , which may or may may not include , is “1” (LRS/HRS), so applying a can change their states to an ON condition (LRS/LRS). Therefore, during the READ time, devices along comprise the ON resistance, , in our simulations. Therefore, for a CRS array, and .
Sizing of the pullup resistor, , as part of the nano domain implementation is a very important factor. For instance, low devices, e.g. magnetic tunneling junctions (MTJs), interconnection impedance should be also taken into account, whereas in ReRAMs, the LRS resistance is normally [23]. Therefore, our approach provides a generalized analytical form for a nanocrossbar array. In other words, if , the nanowire overall resistance will be negligible. These considerations along with taking low output potential, , and high output potential, , lead to an optimal value for . We first follow the conventional approach without considering parasitic currents and the nanowire resistors. Note that in a more precise analysis, the sense amplifier’s sensitivity is also important to be considered [16]. In this situation have,
(9)  
(10) 
where for a memristive array and , whereas for a CRS array and . These equations are applicable for both of the arrays (memristive and CRS array). Read margin (RM) is defined as . An optimal value of can be extracted from . For a memristive array, , where . Taking parasitic resistors into account (e.g. MJTs), and neglecting sneakpaths, results in as an optimal value for the load resistor. For a CRS array,
(11) 
A generalized form can be achieved by solving two Kirchhoff’s current laws (KCLs) for the equivalent circuit (Fig. 5(c)). Therefore, if and
(12)  
(13)  
(14)  
(15) 
where is a memristor or CRS device to be read. This is similar to the ideal condition, , , , and . A numerical approach helps designers to identify an optimal value for . The significance of this analytical model can be highlighted using a comparison between the optimal values for calculated through Eqs. (9) and (10) and the optimal value calculated via Eq. (15) (and if parasitic resistors are negligible then via Eq. (14)). The optimal value for a memristive array, neglecting sneak currents and parasitic resistors, is around using data from Table III. This parameter is a strong function of array size ( and ) and . In practical designs, optimal increases as increases. This rate of change can be significantly reduced by a high . This study shows results in a significant reduction in dependency of the optimum value to the array size. This analytical approach also indicates that in our case for CRS and memristive arrays.
In this paper we calculated the voltage pattern using linear equations from a array. This mathematical framework can be easily implemented using KCL equations in a matrix form. Fig. 6 demonstrates the schematic of how KCL equations work in the two plates. Basically, it shows that for (),
(16)  
(17) 
where , , , , , , and . Therefore, we have unknowns and equations. Depending on the READ scheme, the first and last rows (wordline) and columns (bitline) should be treated differently. Therefore, we can have a control over the voltage pattern and the amount of voltage drop for READ and WRITE operations considering parasitic resistors.
Although, the impact of multiple parasitic currents and nanowire resistors are studied in the literature [43, 2], a comprehensive analytical approach to address these issues, for the both memristive and CRS arrays, is lacking and it is this issue that is addressed in this paper.
Iva Simulations of crossbar array
Extensive analytical studies have been carried out in the area of nano crossbar memory design [2, 41, 43, 42, 40]. Here we extend these studies and also the comprehensive analytical framework, introduced early in this section, to the simulation of the memristive and CRSbased arrays.
For simulations in this paper we consider a range of rectangular array sizes from ,, and () and three input patterns, the best case, the worst case, and a random pattern for sneakpath current, or interference from neighboring cells, considerations. All patterns are identical for memristorbased and CRSbased arrays. Parameter values can be found in Table III and the simulations results are as reported in Table IV for the memory patterns that are given in Fig. 8. If mV is acceptable for the CMOS amplifiers, for memristors and for CRS are acceptable. Only acceptable case for memristor array is the best stored pattern () while all the results for a CRS array are acceptable. This study shows that a memristive array needs substantial improvement in the static power dissipation to be an appropriate candidate for the future memory applications, if values are in the order of k.
For a worst case pattern in a CRSbased array, the bits are initially programmed at their LRS/HRS state (, , and ), which is effectively equivalent to a HRS state. There is only bit on the selected wordline that is programmed with a different logic value and this is for reading and at the same time via different bitlines. Fig. 7 illustrates how a worst case happens by applying appropriate READ voltage (here V) and CRS devices switch to their state, which makes a significant difference in terms of the maximum amount of current that can pass through the device. Consequently, this is the main source of power dissipation for a CRS array. A similar scenario is observed for a array.
Fig. 9 illustrates voltage pattern for a CRS array for reading wordline. The magnitude of the voltage peak above the settled voltage surface for unselected cells shows a successful READ process. A similar approach can be taken for the WRITE process to show that the minimum requirement (at least the programming threshold voltage) is met on the selected cell(s).
Array  ()  Energy (pJ)  
MEM ()  
Worst  V  
Best  V  
Random  V  
Worst  V  
CRS ()  
Worst  V  
Best  V  
Random  V  
Worst  V 
By analyzing the results for a range of array from to , it is observed that to gain an appropriate and nondestructive READ, V, for memristors. This is an intermediate voltage and is low enough to avoid significant change in the device internal state and is high enough to drive a array for the last or worst case selected cells. Our simulations indicate that a relatively high LRS (, as reported in [43]) guarantee enough read margin as well as sufficient potential across a selective cell for a successful WRITE operation when . Therefore, the negative contributions of nanowire parasitic resistors and parasitic (sneak) path currents that are responsible for voltage drop on the selected lines can be both significantly mitigated to a negligible level by increasing and maintaining at a level to guarantee a distinguishable high and low state outputs, whether in terms of or .
Endurance requirement^{3}^{3}3An endurance of is required to replace SRAM and DRAM [1]. There is also an inverse relationship between endurance and data retention. To support reliable large array products, memory technologies must be able to retain data over a long lifetime ( years at C) with a low defect rates. in the CRS will be relaxed by utilizing a nondestructive and scalable readout technique, which significantly reduces the total number of refreshing cycles. A nondestructive readout approach can be found in [44].
IvB Statistical analysis
Recent study on memristive switching behavior indicates that there is also a lognormal (long tail) distribution associated with LRS switching (SET) [23]. This certainly reduces the impact of interconnection resistors due to the fact that a significant portion of low resistor states have higher values than the nominal , however, the impact of such distribution on the device switching speed is significant. The lognormal distribution has been also seen in the switching time ReRAMs [45]. However, despite extensive research about the mechanism that causes the lognormal distribution this area is still under intensive discussion [45].
An analysis has been carried out on a memristive and a CRS arrays through Monte Carlo simulations to observe the impact of the uncertainty associated with , device process variation, spatial randomness of the initial state programming, and unfixed applied voltages. The ON state lognormal distribution data is extracted from [23] while a Gaussian distribution is assumed for the the line edge roughness (LER) for devices, nanowires, and variation on the applied voltages. According to [46], LER and thickness fluctuations is assumed for the both and . We also assumed a normal distribution for initial state programming with . Fig. 10 demonstrates that the CRS array’s output is less sensitive to the overall uncertainty, whereas the memristive array is widely spread out. Minimum value for CRS and memristor arrays are and , respectively. As discussed earlier, for the CRS crosspoint and for the memristor array are acceptable. Table IV has already shown that CRS array stored data pattern sensitivity is much ( times) less than the memristive array. Similarly here, while a memristive array read margin is far less than , a CRS array guarantee margin.
In [46] the impact of such variations defined as , where is either LRS or HRS resistance and the define the thickness fluctuations over LER variation. The HRS resistance in a TiObased memristor is less affected by the overall variation, whereas LRS variation shows a significant deviation from its nominal value. Likewise, since CRS overall resistance of the (unstable) ON state is , so it is less affected by such variation.
IvC Discussion
Results of simulations indicate that the most important parameter that should be increased to achieve higher array sizes for a memristive array is . This research verify that a high () does not necessarily improve the substantial amount of parasitic path currents, while a higher value guarantee a successful READ and WRITE operations.
In a CRSbased crosspoint, the results is more significant since for a high the effective resistance of HRS and LRS are significantly increased. Assuming a high , (), and V, READ operation results in a mV. Analytically, the read margin (RM) does not depend on LRS or HRS resistances and it can be calculated using,
(18) 
which means for a mV limitation ratio should be . Similarly the simulations results show that such high value assumption for , RM is
(19) 
which results () minimum requirement for a successful READ.
Our study also shows that for similar WRITE and READ access time and a high value, energy dissipation ratio of a CRS array over a memristive array constantly increases. This ratio increases rapidly for and (practically) saturates for . The total (static and dynamic) power dissipation for an operation can be calculated using
(20)  
(21) 
where , , , , and are the nano domain, CMOS domain, selected cells, unselected cells, and parasitic elements (nanowires) power dissipations, respectively. We assume that for memristive and CRS arrays are comparable and is negligible. The unselected cells power dissipation can be identified by READ and WRITE schemes and can be divided into two (or more) subclasses of halfselected or unselected cells. This approach helps to identify the memory pattern dependency of the total power dissipation assuming a high .
The READ scheme that is discussed earlier, is used as the first READ scheme. Considering such a scheme and high the total power dissipated by unselected cells (groups (1) and (2) in Fig. 5(a), through sneak currents) is negligible. Therefore, the worst case (reading “1”) power consumption for cells nano in the domain can be calculated through the following equation
(22) 
while similar approach for an CRS array results
(23) 
where in this work V and V. To fill the gap between the power consumption in memristor and CRS arrays and having similar array size (), and , where is a constant that is adjusted to achieve approximately similar power consumption for the two arrays. Here , so for example, K bits of data can be stored either in a memristive array or a CRS array and have roughly similar power dissipation.
In programming (WRITE) procedure, if V and V, there are cells in the both arrays that are halfselected, groups (1) and (3) in Fig. 5(a), and cells that are not selected, ideally V voltage difference, group (2) in Fig. 5(a). The worst case condition is to have all of them at LRS for memristive array and LRS/HRS (logic “1”) for CRSbased crossbar. Therefore, one potential problem with the WRITE scheme is to reset one or more halfselected crosspoints. These cells are categorized under unselected cells for the power calculation. Here, there are V and V potential difference across the halfselected cells in memristor and CRS arrays, respectively, that is sufficiently low to avoid misprogramming. A power consumption analysis for this scheme shows that if and , the total power dissipated in the CRS nano domain is much lower than the memristive array. The main reason is the all of the halfselected cells have an effective resistance equivalent to , whereas the same cells have that is significantly lower. For example, for and overall improvement in power dissipation is around while for results reduction. This improvement rapidly increases if the number of halfselected cells increases. For instance, a WRITE scheme that activates all bitlines (pullup) and wordline (grounded) and applying on the rest of the word lines, can write bits each time and contains halfselected cells.
This study indicates that if , more than and of the total power (and consequently the total energy) is dissipated in halfselected cells during a WRITE operation for the 1bit WRITE and multibit WRITE schemes, respectively. The contribution of halfselected cells is further increased if . The total power consumption is also rapidly increased as the array size increases. The results also indicate that writing a word (multibit) is much more energy efficient than a bit, particularly for CRSbased array. Note that for the multibit WRITE scheme we applied a twostep WRITE operation (SETbeforeRESET) introduced in [47]. The tradeoff between using several WRITE schemes is still an open question.
Due to the fact that a high would decrease the energy dissipation and the operation speed at the same time it is very important to note that the nonlinearity of the memristor characteristics plays an important role in identifying the maximum size constraint of a memristive array by identifying the effect of halfselected memory cells.
Xu et al. [47] proposed a nonlinearity coefficient to analyze the nonlinearity effect using static resistance values of memristor biased at and as . This factor identifies the upper limit for and in a memristive array. If parameter in represents memristor nonlinearity, the factor emphasizes that either higher or higher results in a larger . Clearly, the later option is under the designer’s control. In fact, this technique effectively creates an intermediate , which is larger than its actual value. Note that the resistance does not necessarily increase if increases. There is some examples that do not follow similar characteristics, for instance behavior in [33]. In this case, larger resistances are achievable by decreasing . In [47], is used for bit and wordlines. Considering the scheme, this approach is appropriate when , . For , however, selected wordlines current cannot be calculated with since the current that passes through an unselected cells on a selected wordline is a function of . Hence, calculating an upper limit for is a function of that can be defined as,
(24) 
therefore, a higher nonlinearity coefficient would not necessarily result larger upper limit for memristive array. Furthermore, controlling RESET parameters, such as filament formation process, electrode material, Joule heating process, and TiO composition, plays a key role here.
V Conclusion
The presented work provides a foundation and a generic analytical approach to carry out simulations in the design of future memristivebased circuits and systems in general, and CRS arrays in particular. Simulation results indicate that due to sneakpaths and leakage current, a memristive array is faced with a programming and read error rate that aggressively limit the maximum nanocrossbar array size, whereas a CRS array is less affected by these problems. The read margin in a CRS array is also more robust against technology variations such as uncertainty in initial state programming, nanowire process variation, and the associated uncertainty on low resistance state programming.
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