A Reconfigurable Gate Architecture for Si/SiGe Quantum Dots

A Reconfigurable Gate Architecture for Si/SiGe Quantum Dots

D. M. Zajac Department of Physics, Princeton University, Princeton, NJ 08544, USA    T. M. Hazard Department of Physics, Princeton University, Princeton, NJ 08544, USA    X. Mi Department of Physics, Princeton University, Princeton, NJ 08544, USA    K. Wang Department of Physics, Harvard University, Cambridge, MA 02138, USA Department of Physics, Princeton University, Princeton, NJ 08544, USA    J. R. Petta Department of Physics, Princeton University, Princeton, NJ 08544, USA Department of Physics, University of California, Santa Barbara, CA 93106, USA
July 15, 2019

We demonstrate a reconfigurable quantum dot gate architecture that incorporates two interchangeable transport channels. One channel is used to form quantum dots and the other is used for charge sensing. The quantum dot transport channel can support either a single or a double quantum dot. We demonstrate few-electron occupation in a single quantum dot and extract charging energies as large as 6.6 meV. Magnetospectroscopy is used to measure valley splittings in the range of 35–70 eV. By energizing two additional gates we form a few-electron double quantum dot and demonstrate tunable tunnel coupling at the (1,0) to (0,1) interdot charge transition.

73.21.La, 85.40.-e, 85.35.Gv

Quantum dots have considerable potential for the realization of spin-based quantum devices.loss1998 (); ladd2010 () Extremely long spin coherence timesmuhonen2014 (); steger2012 (); saeedi2013 () and the ability to utilize existing fabrication processes make silicon an attractive host material for quantum dot qubits.veldhorst2014 (); maune2012 (); dohun2014 () Existing depletion mode designs use gate electrode patterns that are much larger than the spatial extent of the resulting electron wavefunctions.stopa2008 () As a result, it is difficult to precisely control the electronic confinement potential. Successful scaling to a larger number of quantum dots will require fine control of the confinement potential on 20 nm length scales. Accumulation mode designs,angus2007 (); borselli2014 () where electrons are accumulated under small positively biased gates (instead of depleted using large “stadium” gate designspetta2005 ()) allow control of the confinement potential on a much smaller length scale and merit further development.

In this letter we present a reconfigurable accumulation mode device architecture that utilizes three overlapping aluminum gate layers. The device architecture has two parallel (and interchangeable) transport channels. One of the channels is used to create single and double quantum dots, while the other channel is used to define a charge sensor quantum dot.barthel2010 () The natural length scale of this gate architecture is comparable to the resulting dot size, allowing a higher degree of control compared to depletion mode devices.petta2005 () Direct local accumulation also reduces capacitive cross-coupling, simplifying the formation of double quantum dots and tuning of the relevant tunnel rates. The architecture demonstrated here provides a straightforward method for scaling to a larger series array of quantum dots, with the required number of gate electrodes in each channel growing linearly as 2+1.

Figure 1: (a) Schematic and cross-sectional transmission electron micrograph showing the growth profile of the heterostructure. An 8 nm Si quantum well is grown on top of a 225 nm SiGe layer, followed by a 50 nm SiGe spacer and a 2 nm protective Si cap. (b) False-color scanning electron micrograph of a device identical to the one measured (see text for details). (c) COMSOL simulation of the electron density in the QW with the gate voltages tuned to form a single dot under L in the upper channel and (d) with a double dot under L and R in the upper channel. In (c–d), the lower channel is configured as a charge sensor, with a single dot formed beneath L.

The device is fabricated on an undoped Si/SiGe heterostructure with the growth profile shown in Fig. 1(a). A SiGe relaxed buffer substrate is grown on a Si wafer by linearly varying the Ge concentration from 0 to 30% over 3 m. The surface of this virtual substrate is then polished before growing an additional 225 nm thick SiGe layer, followed by an 8 nm Si quantum well (QW), a 50 nm SiGe spacer and a 2 nm protective Si cap. The Si QW is uniaxially strained by the Si/SiGe lattice mismatch, breaking the six-fold valley degeneracy.ando1982 (); schaffler1997 () The degeneracy of the two lowest lying valleys is further lifted by quantum confinement in the growth direction.boykin2004 () Accumulation mode Hall bar samples fabricated on this wafer yield a two-dimensional electron gas (2DEG) carrier mobility = cm/Vs at an electron density = /cm and temperature = 350 mK. A valley splitting = 170 eV is measured at a magnetic field = 1.75 T. The 2DEG also undergoes a metal-to-insulator transition (MIT) at a critical density of /cm. Both the high electron mobility and low critical density of the MIT are indicative of low disorder in the 2DEG.xiao2015 ()

Electronic confinement in the plane of the QW is achieved using three overlapping layers of Al gate electrodes, as shown in Fig. 1(b). Overlapping gates allow full control of the confinement potential since no region of the Si surface is left exposed. In addition, the potential is tuned on a 20 nm length scale, limited by the resolution of the electron beam lithography tool. The first layer of aluminum, shown in light blue, serves as a screening layer, and its purpose is to selectively screen out the electric fields formed by the accumulation gates in layers 2 and 3. The result is two parallel transport channels that cross the device from left to right. The second Al layer, shown in red, consists of two plunger gate electrodes in the upper channel (labelled L and R) and lower channel (labelled L and R). Source and drain accumulation gates (S and D, respectively) are also defined in layer 2 and are typically biased at 700 mV to create a Fermi sea of electrons that extends out to implanted ohmic contacts. Layer 3, shown in green, consists of three gate electrodes per channel, labelled LB, MB, and RB, which are designed to control tunnel barrier heights. A controlled oxidation process is performed after the metallization of each layer to create a thin insulating oxide around the gates, which electrically isolates them from subsequent gate layers.lim2009 (); lim0929 ()

Given the symmetry of the design, the upper and lower transport channels are interchangeable. In what follows, we utilize the lower channel to form a charge sensor quantum dot that is sensitive to the electron occupancy of the quantum dots formed in the upper channel. To form the sensor quantum dot we first raise the voltages on all gates in the lower channel until conductance is measured through the channel. The gate voltages and are then lowered to form tunnel barriers, resulting in a single quantum dot under L. A single quantum dot is formed in the upper channel by performing the same procedure, resulting in a single quantum dot under L. is then decreased until we achieve few-electron occupancy. The carrier density for this gate voltage configuration is simulated using COMSOL Multiphysics software,schmidt2014 () as shown in Fig. 1(c). In principle, an additional quantum dot can be formed under R by lowering . Again is decreased to reduce the electron occupation in the right dot resulting in the simulated carrier density shown in Fig. 1(d).

Figure 2: (a) The derivative of the charge sensor conductance plotted as a function of and reveals the charge stability diagram of the single quantum dot formed under L. (b) Energy level diagram of a quantum dot with a low-lying valley state plotted as a function of , where is the Zeeman energy and is the valley splitting. The red line shows the expected spin filling of the = 1 to 2 charge transition as a function of . (c) Magnetospectroscopy at the = 0 to 1 charge transition is consistent with spin-down filling. (d) Magnetospectroscopy at the = 1 to 2 charge transition indicates a crossover from spin-up filling to spin-down filling when = .

We now show that this gate architecture is capable of reaching the few electron regime in both single and double dot modes of operation. The device is characterized in a dilution refrigerator with an electron temperature = 40 mK. We first form a single lead quantum dot in the upper channel using gate L as a plunger and gate LB to control the tunnel barrier height. Charge sensing is achieved by forming a single dot in the lower channel under L using LB and MB as barriers. The charge sensor quantum dot is biased on the edge of a Coulomb blockade peak, where the dot conductance is highly sensitive to changes in the local electrostatic potential.elzerman2003 () Figure 2(a) shows a charge stability diagram obtained by plotting the derivative of the charge sensor conductance dd as a function of the voltages and . is linearly compensated as and are swept to keep the dot biased on the edge of the Coulomb blockade peak. The absence of charge transitions in the lower left corner of the plot indicates that we have reached the = 0 charge state.

Tight electronic confinement is important in Si quantum devices since the effective mass is approximately three times larger than in GaAs. We can estimate the size of the accumulation mode quantum dots from measurements of the charging energy. The spacing between the first two charge transitions in Fig. 2(a) is = 60 mV. Taking into account the lever-arm conversion between gate voltage and energy eV/V, this yields a charging energy of 6.6 meV. We estimate the dot size from the capacitance using a disk capacitor model. From the charging energy we extract a capacitance of aF where is the charging energy,kouwenhoven1997 () giving a dot radius of nm where and F/m. This is consistent with the dot radius of 30 nm that is predicted using COMSOL. Pulsed-gate spectroscopy dataelzerman2004 () (not shown) yields an orbital energy = 2.5 meV for the = 1 charge state, which is also consistent with a dot size of = 29 nm for a particle in a 2D box. By setting the area of the disk equal to the area of a 2D square box with side ( = ), we expect an orbital energy of meV where is the reduced Planck’s constant, = 0.19 , and is the free electron mass.schaffler1997 () Lastly, Fig. 2(a) indicates that is very effective at tuning the tunnel rate to the source lead of the dot. For example, the = 0 to 1 and = 1 to 2 charge transitions show “latching” in the lower left region of the plot when the barrier tunneling rate becomes comparable to the rate at which the gate voltage is rastered. Transitions in the upper right region of the charge stability diagram become lifetime broadened when , here is Boltzmann’s constant and is Planck’s constant.de2001 ()

Unlifted valley degeneracy will introduce orbital decoherence and weaken Pauli blockade, which is used for spin readout in spin-to-charge conversion.elzerman2004 () It is therefore important to understand the level structure of the quantum dots. Figure 2(b) schematically shows the energy level diagram of a single quantum dot as a function of for a relatively small .lim2011 () At = 0 there are two spin degenerate valleys separated by . Application of a magnetic field results in Zeeman splitting =, lifting the spin degeneracy. Here is the g-factor of electrons in silicon and is the Bohr magneton. Electrons will fill the lowest energy states as they are added to the dot. The red line shows the expected filling of the second electron as a function of . The kink represents the point at which = , where the spin state of the loaded electron is expected to change from spin-up to spin-down. Figures 2(c) and (d) show magnetospectroscopyborselli2011 (); yang2012 () data taken at the = 0 to 1 and = 1 to 2 transitions in the dot formed under L. The derivative of the charge sensor conductance dd is plotted as a function of and . The presence of a kink in Fig. 2(d) is consistent with the red line shown in Fig. 2(b) indicating a change from spin-up filling to spin-down filling at T. From the lever arm eV/V and the slope of the charge transition in Fig. 2(c) we measure a g-factor of =1.9 0.1 and extract a valley splitting of = 35 eV for this dot. Single lead quantum dots were also formed under gates R, L, and R by reconfiguring the device (data not shown here) yielding valley splittings of 35 eV, 60 eV, and 70 eV.

Figure 3: Evolution of the charge stability diagram as a function of . Charge stability diagrams obtained by sweeping and are shown for: (a) = 200 mV, (b) = 0 mV, (c) = -200 mV, and (d) = -500 mV. As decreases a new dot is formed under L, converting the single quantum dot into a double quantum dot. Insets show COMSOL simulations of the electron density in the QW.

Device tuning requires control of a multi-dimensional parameter space.granger2010 () In depletion mode devices there is significant cross-capacitance between gateshanson2007 () which complicates this task. The cross capacitance of adjacent gates can be extracted from the slope of the charge transitions in single dot charge stability diagrams. For example, the data of Fig. 2(a) yield a capacitance ratio of 19%, in reasonable agreement with COMSOL predictions (12% cross capacitance for these gates). The small cross-coupling allows a single dot in the upper channel to be easily converted into a double quantum dot by changing a single gate voltage.

Figure 3 (a–d) show charge stability diagrams that are obtained by sweeping and . In Fig. 3(a) = 200 mV and a single dot is formed under the right plunger gate, R. A tunnel barrier is then formed under LB as its voltage is made more negative, converting the single quantum dot into a double quantum dot. At = 0 mV a dot begins to form under L as indicated by the appearance of lifetime broadened charge transitions, see Fig. 3(b). Further reducing strengthens Coulomb blockade, resulting in sharper left dot charge transitions. A clean double dot stability diagram is obtained in Fig. 3(d) for = -500 mV. Insets in each panel show the calculated electron densities for different values of and serve to illustrate the evolution of the 2DEG at different stages of tuning.

Figure 4 shows a high resolution double dot charge stability diagram. Here is linearly compensated to stay on the edge of a Coulomb blockade peak while and are swept. The absence of charge transitions in the lower left corner of the plot indicates that we have reached the (0,0) charge configuration, where (,) denotes the occupancy of the left and right dots. The left and right dot charge transitions show very little curvature, indicating that the confinement potential is well defined by our gate pattern and not significantly affected by the capacitive coupling of the two dots. From the slope of a left dot charge transition we extract a right plunger to left plunger capacitance ratio of 24%, which is considerably smaller than the 55% coupling measured in a dual-gate architecture.wang2013 ()

Figure 4: Double quantum dot charge stability diagram showing few-electron occupation. Inset: The probability of being in the (0,1) charge configuration is plotted as a function of detuning at the (1,0)-(0,1) charge transition for different values of showing tunable interdot tunnel coupling.

The ability to tune the tunnel coupling between two dots is an important requirement for spin-based quantum dot qubits.divincenzo2000 () First, it demonstrates control of the confinement potential on short length scales. Second, the interdot tunnel coupling sets the double dot exchange energy loss1998 (). The Hamiltonian at the (1,0)-(0,1) charge transition is given by where is the detuning, is the interdot tunnel coupling and are the Pauli matrices.kouwenhoven2002 () We demonstrate tunable interdot tunnel coupling in the inset of Fig. 4, which shows the probability of being in the (0,1) charge state as a function of for three different values of . The detuning axis is shown in the main panel of Fig. 4. These data are fit to the expression


where 40 mK is the electron temperature and is the energy difference of the hybridized charge states.dicarlo2004 (); petta2004 (); simmons2009 () For = 285 mV, and the transition is thermally broadened. For = 360 and 385 mV values of = 5 eV and 15 eV are extracted by fitting the data to Eq. (1). For higher values of we observe tunnel couplings exceeding 100 eV.

In conclusion we have demonstrated a reconfigurable device architecture for Si/SiGe that allows the formation of single and double quantum dots. In single dot mode, we extract charging energies as large as 6.6 meV, orbital energies of 2.5 meV, and valley splittings in the range of 35 – 70 eV. With the same device, we have formed a few electron double quantum dot, demonstrating tunable interdot tunnel coupling. The overlapping gate architecture provides a path forward for scaling to larger series arrays of quantum dots.

Research was sponsored by the United States Department of Defense with partial support from the NSF (DMR-1409556 and DMR-1420541). The views and conclusions contained in this letter are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the United States Department of Defense or the U.S. Government.


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